A 12 Gb/s 0.9 mW/Gb/s Wide-Bandwidth Injection-Type CDR in 28 nm CMOS With Reference-Free Frequency Capture

Masuda, Takashi; Shinoda, Ryota; Chatwin, Jeremy; Wysocki, Jacob; Uchino, Koki; Miyajima, Yoshifumi; Ueno, Yosuke; Maruko, Kenichi; Zhou, Zhiwei; Suzuki, Hideyuki; Shoji, Norio

doi:10.1109/jssc.2016.2594077

Cited by 23 publications

(4 citation statements)

References 3 publications

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“…To perform high-resolution phase generation, we employed an analog, inverter-based PI based on previous works [42][43][44][45][47][48][49][50][51][52][53][54] in the proposed BBCDR. Despite its intrinsic phase capture range limitation, this topology is preferable to digital PIs [42][43][44]48,49 for its intrinsic simplicity, adjustable output phase, and low power.…”

Section: Pimentioning

confidence: 99%

A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation

Wang

Chen

Yang

et al. 2023

Circuit Theory & Apps

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This paper reports a bang-bang clock and data recovery circuit (BBCDR) with an ultra-wide capture range. The circuit exhibits automatic frequency capture and phase locking over a wide 6-to-38 Gb/s range without using a frequency detector, allowed by a recently proposed deliberate-current-mismatch technique. Moreover, we accurately obtain an eight-phase clock through analog interpolation of quadrature signals over the whole wide frequency range by introducing a tunable capacitor array before an inverter-based phase interpolator. A 65-nm prototype of the developed BBCDR occupies an area of 0.07 mm 2 and attains a bit error rate of less than 10 À12 under a continuously variable input frequency, with a total power consumption of 24.6 mW for a 32-Gb/s non-return-zero input, thus leading to 0.769-pJ/bit energy efficiency.bang-bang clock and data recovery (BBCDR), current mismatch, frequency detector (FD), hybrid control circuit (HCC), phase interpolator (PI), ring oscillator (RO), R-2R digital-toanalog converter (DAC), switched-capacitor (SC) array, wide capture range

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Section: Pimentioning

confidence: 99%

A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation

Wang

Chen

Yang

et al. 2023

Circuit Theory & Apps

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show abstract

“…In order to prevent this phenomenon, channel coding that guarantees maximum run‐length is required. The channel coding method usually used two types of data encoding schemes: embedded clock with dummy clock bits 10 or enclosed transition density with data encoding such as 8B10B encoding 11,12 . However, these channel coding methods reduce the effective bandwidth by 11% or more.…”

Section: The Purpose Of Channel Codingmentioning

confidence: 99%

“…The channel coding method usually used two types of data encoding schemes: embedded clock with dummy clock bits 10 or enclosed transition density with data encoding such as 8B10B encoding. 11,12 However, these channel coding methods reduce the effective bandwidth by 11% or more. Therefore, there is a need for a channel coding method that minimizes the decrease in effective bandwidth.…”

Section: The Purpose Of Channel Codingmentioning

confidence: 99%

A clock embedded intra‐panel interface with 1.96% data overhead for beyond 8K displays

et al. 2023

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This paper proposes a 6Gb/s receiver for 8K displays and beyond. In the proposed receiver, a novel channel coding with 1.96% overhead is presented to guarantee minimum run-length in the clock embedded interface. It can also reduce bandwidth for effective data transmission compared to 9b/10b coding that requires 11.11% overhead. Furthermore, we present an on-chip eye margin tester that can measure the internal timing margin of receiver with only 1% area overhead. The prototype ICs are implemented using 0.18-μm HVCMOS process and evaluated in an 8K 65-in. panel.

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“…ADCDRs are derived from the first All-Digital Phase Locked Loop (AD-PLL) introduced in [13] and comprise a phase detector and a digital controlled oscillator in addition to a digital loop filter [2]- [4], [14]- [18]. PLL-based CDR circuits have the advantage over alternative digital friendly CDRs that they have intrinsically a wide frequency capture range due to the ability to adapt both phase and frequency [19]. Additionally, they benefit from a wide bandwidth and have the ability to reject input jitter [20].…”

Section: Introductionmentioning

confidence: 99%

A 1.8-pJ/b, 12.5–25-Gb/s Wide Range All-Digital Clock and Data Recovery Circuit

Verbeke

Rombouts

Ramon

et al. 2018

IEEE J. Solid-State Circuits

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Abstract-Recently, there has been a strong drive to replace established analog circuits for multi-gigabit Clock and Data Recovery (CDR) by more digital solutions. We focused on PLLbased All-Digital CDR (AD-CDR) techniques which contain a Digital Loop Filter (DLF) and a Digital Controlled Oscillator (DCO) and pushed the digital integration up to a level where our DLF is entirely synthesized. To enable this, we found that extensive subsampling can be used to decrease the speed of the DLF while maintaining a good operation. Additionally, an Inverse Alexander phase detector and a 5.5-bit resolution DCO complete the AD-CDR architecture. As a result of the low-complexity and digital architecture, the AD-CDR occupies a compact active chip area of 0.050mm 2 and consumes only 46mW at 25Gb/s. This is the smallest area and lowest power consumption compared to the state-of-the-art. In addition, our implementation is highly tunable due to the synthesized logic and supports a wide operating range (12.5Gb/s-25Gb/s), which is a significantly larger range compared to previous work. Finally, thanks to our digital architecture the power dissipation decreases linearly while moving to the lower speeds of our operating range. This is in contrast with most prior work, making our design truly adaptive.

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A 12 Gb/s 0.9 mW/Gb/s Wide-Bandwidth Injection-Type CDR in 28 nm CMOS With Reference-Free Frequency Capture

Cited by 23 publications

References 3 publications

A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation

A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation

A clock embedded intra‐panel interface with 1.96% data overhead for beyond 8K displays

A 1.8-pJ/b, 12.5–25-Gb/s Wide Range All-Digital Clock and Data Recovery Circuit

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