A 12-Bit Low-Input Capacitance SAR ADC With a Rail-to-Rail Comparator

A Reconfigurable Hybrid ADC Using a Jump Search Algorithm

“…In refs. [15,20], they achieve an 8-11% higher ENOB than the 12-bit mode of this design. However, in ref.…”

“…In ref. [20] it operates at roughly twice the speed (1 MS/s), but, due to the bootstrap S/H circuit, it consumes 8 times more power than this design, resulting in this design having a better FoM. In ref.…”

“…However, in refs. [15,[18][19][20], the ADCs are based on the SAR-SS and SAR ADC architectures. In refs.…”

“…Among recently researched ADCs [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20], various hybrid structures [11][12][13][14][15][16][17][18][19] are being explored. However, the SAR ADC architecture is required due to the low power consumption, bandwidth, and resolution for biomedical signal processing.…”

“…Lastly, the 12-bit SAR ADC in [20] with the S/H block is separated from the C-DAC to address the high input capacitance of conventional SAR ADCs. It reduces the offset by controlling the gain of the comparator in the S/H block to mitigate the nonlinear inputrelated offset and kickback noise caused by the variations in the input common-mode voltage of the comparator.…”