A 12-bit current steering DAC with 2-dimensional gradient-error tolerant switching scheme

Abstract

A 12-bit intrinsic accuracy digital-to-analog converter integrated into standard digital 0.18 m CMOS technology is proposed. It is based on a current steering segmented 6+6 architecture and requires no calibration. By dividing one most significant bit unary source into 16 elements located in 16 separated regions of the array, the linear gradient errors and quadratic errors can be averaged and eliminated effectively. A novel static performance testing method is proposed. The measured differential nonlinearity and integral nonlinearity are 0.42 and 0.39 least significant bit, respectively. For 12-bit resolution, the converter reaches an update rate of 100 MS/s. The chip operates from a single 1.8 V voltage supply, and the core die area is 0.28 mm 2 .

A Low-Power Column-Parallel Gain-Adaptive Single-Slope ADC for CMOS Image Sensors

“…A 12-bit current steering DAC with 6+6 architecture and two-dimensional gradient error tolerant switching scheme [21] is adopted as the ramp generator to improve the linearity of the ADC. The block diagram of the ramp generator is shown in Figure 15.…”

A survey of high-speed high-resolution current steering DACs

“…In the design of current steering DACs, the main challenge is to reduce the impact of static and dynamic errors. The static errors mainly come from the amplitude mismatch of current sources [21] , which are caused by random errors and systematic errors [22] . In a given process technology, increasing the device size appropriately is an effective method for reducing random errors.…”

“…However, systematic errors might be generated due to the large area [23] . To compensate the gradient errors, switching sequence optimization is a commonly used scheme [22,23] . As the static performance of a segmented DAC is strongly dependent on the most significant bits (MSB) which are thermometer encoded, a suitable segmentation is also essential.…”