A 12-b 40-MS/s Calibration-Free SAR ADC

Hsu, Chia-Yang; Chang, Soon-Jyh; Huang, Chun-Po; Chang, Li-Jen; Shyu, Ya-Ting; Hou, Chih-Huei; Tseng, Hwa-An; Kung, Chih-Yuan; Hu, Huan-Jui

doi:10.1109/tcsi.2017.2771364

Cited by 18 publications

(4 citation statements)

References 5 publications

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“…The FOM of the proposed SAR ADC was 32.84 fJ/ conversion-step using the above equation. Table 2 displays the comparison with other state-of-the-art SAR ADCs having conversion rate >10 MS/s [4,5,[13][14][15][16][17][18].…”

Section: Resultsmentioning

confidence: 99%

1.2 V 10‐bits 40 MS/s CMOS SAR ADC for low‐power applications

Huang

2019

IET Circuits, Devices & Systems

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This article presents a 10-bits low-power successive approximation register analogue-to-digital converter (SAR ADC). The dual sampling technique was applied to the capacitive digital-to-analogue converter (CDAC), and the CDAC structure was constructed using a binary-weighted capacitor array and a C-2C capacitor array, simultaneously. Consequently, the CDAC structure enabled low-power consumption and a small layout area for the proposed SAR ADC. Moreover, the rail-to-rail operation of the bootstrapped circuit enabled the low-voltage ADC to be implemented, thereby improving the non-linearity. A prototype was designed and implemented using TSMC 0.18 μm CMOS 1P6M technology. This design achieved differential nonlinearity and integral non-linearity of 0.36 least significant bit (LSB) and 0.45 LSB, respectively, and a signal-to-noise-anddistortion ratio of 56.7 dB and spurious-free dynamic range of 65.8 dB at the input frequency of 2 MHz. At a sampling rate of 40 MS/s with a single 1.2 V power supply, the power consumption was 736 μW. The proposed ADC achieved a figure-of-merit of 32.84 fJ/conversion-step. The ADC core occupied an active area of 195 × 241 μm 2 .

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Section: Resultsmentioning

confidence: 99%

1.2 V 10‐bits 40 MS/s CMOS SAR ADC for low‐power applications

Huang

2019

IET Circuits, Devices & Systems

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“…The sampling rate should be on the same order as the DAC. As an example of an ADC that can be used, in [24], a 10 MS/s calibration-free ADC with 11 effective number of bits (ENOB) is presented, consuming 0.41 mW and occupying 0.04mm 2 . Reducing the rate to kS/s should provide significant power reductions, making the impact of the ADCs on the total power consumption negligible.…”

Section: Injection-locked Phase Shifter and Phase Detectormentioning

confidence: 99%

An LO phase shifter with frequency tripling and phase detection in 28 nm FD-SOI CMOS for mm-wave 5G transceivers

Gannedahl

Sjöland

2023

Analog Integr Circ Sig Process

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This paper presents an LO phase shifter with frequency tripling for 28-GHz 5G transceivers. The phase shifting and frequency tripling are achieved using an injection-locked oscillator and injection-locked frequency tripler, respectively. A phase detector based on third harmonic mixing is also implemented and is used to detect the applied phase shift, supporting automatic calibration of the phase shifter. Additionally, an algorithm to automatically tune the oscillators to their respective locking frequency is presented. To test the phase shifter, a 24–30-GHz sliding-IF receiver is implemented. Simulations show that a > 360$$^\circ $$ ∘ tuning range over the full 24–30 GHz span is achieved, with a gain variation of 0.11 dB or less, and that the phase detector has an rms phase error of < 2.5$$^\circ $$ ∘ . The circuit is implemented in a 28nm FD-SOI CMOS process and the entire chip measures 1080 $$\upmu \hbox {m}$$ μ m $$\times $$ × 1080 $$\upmu \hbox {m}$$ μ m , including pads, and consumes 27–29 mW from a 1 V supply.

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“…However, as the resolution exceeds 10 bits, the accuracy of the SAR ADC is affected by capacitance mismatch, comparator noise and offset, etc. [9][10][11][12]. To mitigate comparator offset, three techniques are employed: trimming, chopping and auto-zeroing.…”

Section: Introductionmentioning

confidence: 99%

A Power-Efficient 16-bit 1-MS/s Successive Approximation Register Analog-to-Digital Converter with Digital Calibration in 0.18 μm Complementary Metal Oxide Semiconductor

He,

Qiao,

Xing

et al. 2024

JLPEA

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A power-efficient 16-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. High-bit sampling makes the bridge capacitance in the digital-to-analog converter (DAC) a unit one, eliminating fractional capacitance mismatch. The high-precision comparator is composed of a four-stage preamplifier and a strong-arm latch, with auto-zeroing used to mitigate input offset further. Digital foreground calibration based on low-bit weight is implemented to correct DAC capacitance mismatch. The post-layout simulation results show that the core ADC achieves 95.61 dB SNDR and 105.1 dB SFDR with calibration, consuming 5.4 mW power under a 3.3 V supply voltage, corresponding to a Schreier figure of merit (FoM) of 175.3 dB. The ADC core area is 1.06 mm2 in the 180 nm CMOS technology.

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A 12-b 40-MS/s Calibration-Free SAR ADC

Cited by 18 publications

References 5 publications

1.2 V 10‐bits 40 MS/s CMOS SAR ADC for low‐power applications

1.2 V 10‐bits 40 MS/s CMOS SAR ADC for low‐power applications

An LO phase shifter with frequency tripling and phase detection in 28 nm FD-SOI CMOS for mm-wave 5G transceivers

A Power-Efficient 16-bit 1-MS/s Successive Approximation Register Analog-to-Digital Converter with Digital Calibration in 0.18 μm Complementary Metal Oxide Semiconductor

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