A −117dBc THD (−132dBc HD3) and 126dB DR Audio Decoder with Code-Change-Insensitive RT-DEM Algorithm and Circuit Technique for Relaxing Velocity Saturation Effect of Poly Resistors

Wen, Shon-Hang; Hsiao, Chuan-Hung; Chien, Shih-Hsiung; Chen, Ya-Chi; Chen, Kuan‐Hung; Chen, Kuan-Dar

doi:10.1109/isscc42614.2022.9731634

Cited by 4 publications

(2 citation statements)

References 2 publications

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“…Unit-element mismatch within the two sub-DACs is addressed with real-time (RT) DEM [6], which produces no idle tones and achieves better SNDR at the chosen OSR (=19.2) than data-weighted averaging (DWA). Furthermore, since the DAC elements are driven by a PWM-like signal, their individual mismatch contribution is reduced at small input levels as the dutycycle of their PWM inputs approaches 50%.…”

Section: Green Open Access Added To Tu Delft Institutional Repositorymentioning

confidence: 99%

“…Furthermore, since the DAC elements are driven by a PWM-like signal, their individual mismatch contribution is reduced at small input levels as the dutycycle of their PWM inputs approaches 50%. With RTDEM, however, code changes larger than 1 may cause nonlinear ISI [6], which will happen quite often since the DAC input is chopped. In this work, this source of nonlinearity is also eliminated by the DB.…”

Section: Green Open Access Added To Tu Delft Institutional Repositorymentioning

confidence: 99%

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3.1 A 120.9dB DR, -111.2dB THD+N Digital-Input Capacitively-Coupled Chopper Class-D Audio Amplifier

Zhang

Berkhout²,

Makinwa

et al. 2023

2023 IEEE International Solid- State Circuits Conference (ISSCC)

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Class-D amplifiers (CDAs) are widely used in audio applications where a high power efficiency is required. As most audio sources are digital nowadays, implementing digitalinput CDAs results in higher levels of integration and lower cost. However, prior open-loop digital-input CDAs suffer from high jitter sensitivity and output-stage distortion. In [1], jitter sensitivity at small signal levels is mitigated using a buck-boost converter that adaptively lowers the supply at the expense of extra external components and reduced power efficiency. Prior closed-loop digital-input CDAs employing multi-bit current-steering [2] or resistive [3] DACs are less sensitive to jitter, but their DR is limited to about 115dB. DAC non-idealities and intermodulation distortion are also challenges, and prior works only achieved a peak THD+N of about −98dB [2,3]. This paper presents a digital-input CDA that achieves high DR by combining a low-noise capacitive DAC (CDAC) with dedicated techniques to mitigate DAC mismatch, ISI, and intermodulation distortion. A prototype implemented in a 0.18μm BCD process achieves 120.9dB DR and −111.2dB peak THD+N. Furthermore, it can deliver 13W/23W at 10% THD into an 8Ω/4Ω load with a 90%/86% efficiency.

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Section: Green Open Access Added To Tu Delft Institutional Repositorymentioning

confidence: 99%

Section: Green Open Access Added To Tu Delft Institutional Repositorymentioning

confidence: 99%

3.1 A 120.9dB DR, -111.2dB THD+N Digital-Input Capacitively-Coupled Chopper Class-D Audio Amplifier

Zhang

Berkhout²,

Makinwa

et al. 2023

2023 IEEE International Solid- State Circuits Conference (ISSCC)

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Bandpass Filter and Oscillator ICs with THD < -140dBc at 10V_ppd for Testing High-Resolution ADCs

Sarkar

Agarwal

Krishnapura

2023

2023 IEEE International Solid- State Circuits Conference (ISSCC)

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21.4 A -108dBc THD+N, 2.3mW Class-H Headphone Amplifier with Power-Aware SIMO Supply Modulator

Wen,

Hsiao,

Huang

et al. 2024

2024 IEEE International Solid-State Circuits Conference (ISSCC)

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A −117dBc THD (−132dBc HD3) and 126dB DR Audio Decoder with Code-Change-Insensitive RT-DEM Algorithm and Circuit Technique for Relaxing Velocity Saturation Effect of Poly Resistors

Cited by 4 publications

References 2 publications

3.1 A 120.9dB DR, -111.2dB THD+N Digital-Input Capacitively-Coupled Chopper Class-D Audio Amplifier

3.1 A 120.9dB DR, -111.2dB THD+N Digital-Input Capacitively-Coupled Chopper Class-D Audio Amplifier

Bandpass Filter and Oscillator ICs with THD < -140dBc at 10V_ppd for Testing High-Resolution ADCs

21.4 A -108dBc THD+N, 2.3mW Class-H Headphone Amplifier with Power-Aware SIMO Supply Modulator

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A −117dBc THD (−132dBc HD3) and 126dB DR Audio Decoder with Code-Change-Insensitive RT-DEM Algorithm and Circuit Technique for Relaxing Velocity Saturation Effect of Poly Resistors

Cited by 4 publications

References 2 publications

3.1 A 120.9dB DR, -111.2dB THD+N Digital-Input Capacitively-Coupled Chopper Class-D Audio Amplifier

3.1 A 120.9dB DR, -111.2dB THD+N Digital-Input Capacitively-Coupled Chopper Class-D Audio Amplifier

Bandpass Filter and Oscillator ICs with THD < -140dBc at 10Vppd for Testing High-Resolution ADCs

21.4 A -108dBc THD+N, 2.3mW Class-H Headphone Amplifier with Power-Aware SIMO Supply Modulator

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Product

Resources

About

Bandpass Filter and Oscillator ICs with THD < -140dBc at 10V_ppd for Testing High-Resolution ADCs