A 113 mm/sup 2/ 600 Mb/s/pin 512 Mb DDR2 SDRAM with vertically-folded bitline architecture

Kirihata, T.; Mueller, Georg; Clinton, Michael; Loeffler, Steffen; Ji, Bing; Terletzki, H.; Hanson, David R.; Hwang, Chorng-Lil; Lehmann, G.; Storaska, D.; Daniel, George; Hsu, L.; Weinfurtner, O.; Boehler, T.; Schnell, Josef; Frankowsky, G.; Netis, D.; Ross, Joe; Reith, A.M.; Kiehl, Oliver; Wordeman, M.R.

doi:10.1109/isscc.2001.912683

Cited by 7 publications

(3 citation statements)

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“…Dense DRAM have smaller cell area, which is 6.6F 2 demonstrated by [15]. Although XPT MRAM cell is as small as 1.5F 2 [10], using the current Spin-Torque Transfer (STT) technology, the size of a 1T1J MRAM cell in this paper is 8.4F × 4.4F , which is 5.6X larger than the densest DRAM.…”

Section: Stacking Mram As Replacement Of Main Memorymentioning

confidence: 85%

Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement

Dong

Sun

et al. 2008

Proceedings of the 45th Annual Design Automation Conference

271

115

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Magnetic Random Access Memory (MRAM) has been considered as a promising memory technology due to many attractive properties. Integrating MRAM with CMOS logic may incur extra manufacture cost, due to its hybrid magnetic-CMOS fabrication process. Stacking MRAM on top of CMOS logics using 3D integration is a way to minimize this cost overhead. In this paper, we discuss the circuit design issues for MRAM, and present the MRAM cache model. Based on the model, we compare MRAM against SRAM and DRAM in terms of area, performance, and energy. Finally we conduct architectural evaluation for 3D microprocessor stacking with MRAM. The experimental results show that MRAM stacking offers competitive IPC performance with a large reduction in power consumption compared to SRAM and DRAM counterparts.

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Section: Stacking Mram As Replacement Of Main Memorymentioning

confidence: 85%

Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement

Dong

Sun

et al. 2008

Proceedings of the 45th Annual Design Automation Conference

271

115

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“…Dynamic RAMs [1][2][3][4] basically consist out of a charge storing capacitor which is accessed via an array device (Fig. 2).…”

Section: Dynamic Ramsmentioning

confidence: 99%

Memory-Technologies: Pace-Setters for the IC-Industry

Klose

Dehm²,

Mueller³

et al. 2001

31st European Solid-State Device Research Conference

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“…The higher data rate, however, increases the junction temperature and causes thermal runaway in the worst case. In order to avoid the problem associated with increased data rate, JEDEC has standardized DDR-II SDRAM, targeting 533 Mb/s/pin at much lower supply voltage than DDR SDRAM and RAMBUS DRAM [4]- [6]. DDR-II SDRAM is specified to operate with 1.8-V supply voltage while DDR SDRAM and RAMBUS DRAM use 2.5-V supply voltage.…”

Section: Introductionmentioning

confidence: 99%

A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration

Yoo

Kyung

Han

et al. 2004

IEEE J. Solid-State Circuits

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A 512-Mb DDR-II SDRAM has achieved 700-Mb/s/pin operation at 1.8-V supply voltage with 0.12-m DRAM process. The low supply voltage presents challenges in high data rate and signal integrity. Circuit techniques such as hierarchical I/O lines, local sense amplifier, and fully shielded data lines without area penalty have provided improved data access time and, thus, high data rate can be achieved. Off-chip driver with calibrated strength and on-die termination are utilized to give sufficient signal integrity for over 533-Mb/s/pin operation. Index Terms-CMOS, DDR-II, double data rate (DDR), DRAM, hierarchical I/O line, local sense amplifier, low voltage, off-chip driver, on-die termination, SDRAM.

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A 113 mm/sup 2/ 600 Mb/s/pin 512 Mb DDR2 SDRAM with vertically-folded bitline architecture

Cited by 7 publications

References 0 publications

Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement

Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement

Memory-Technologies: Pace-Setters for the IC-Industry

A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration

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