A 110dB SNR and 0.5mW current-steering audio DAC implemented in 45nm CMOS

Hezar, Rahmi; Risbo, Lars; Kiper, Halil; Fares, Mounir; Haroun, Baher; Burra, G.; Gomez, Gabriel

doi:10.1109/isscc.2010.5433891

Cited by 10 publications

(7 citation statements)

References 2 publications

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“…The optimal bias current I D of the OTA is then computed by substituting t slew into either (2) or (3).…”

Section: Circuit Implementation 1 Digital Front-endmentioning

confidence: 99%

“…Recently, as the market for artificial intelligent speakers has expanded and become popular, high-quality audio coder-decoder (CODEC) is required. The deltasigma (ΔΣ) digital-to-analog converter (DAC), one of the key components of the CODEC, is essential for generating high-performance audio signals with a signalto-noise ratio (SNR) over 100 dB [1][2][3]. An anti-aliasing filter (AAF) is needed to reduce out-of-band noise (OBN).…”

Section: Introductionmentioning

confidence: 99%

“…It produces an analog audible signal and filters OBN. There are two ways to implement: a current-steering [2,3] and a switched-capacitor (SC) [9,10]. The current-steering type has the advantages of low-power consumption and small area, but it is very sensitive to clock jitter.…”

Section: Introductionmentioning

confidence: 99%

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A Stereo Audio Delta-Sigma DAC with 40-kHz Bandwidth and 103-dB SNR

Yang¹,

Cho²,

Park³

et al. 2018

JSTS

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A wide-band and low-noise stereo deltasigma (ΔΣ) digital-to-analog converter (DAC) for audio applications is proposed. A multi-bit quantizer with data-weighted averaging is used to reduce quantization noise and a half-band finite impulse response filter is designed to increase the speed of the ΔΣ modulator. A direct-charge-transfer switchedcapacitor DAC and a track-and-hold circuit with a deglitch timing are used to improve the operating speed and the linearity of the audio DAC. The chip is fabricated with a 0.13-μm CMOS process, which uses the supply voltages of 1.2 V for the digital domain and 3.3 V for the analog domain. The experimental results show that our audio DAC achieves 40-kHz bandwidth, 103-dB A-weighted signal-to-noise ratio, and-85-dB total harmonic distortion and noise.

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“…The optimal bias current I D of the OTA is then computed by substituting t slew into either (2) or (3).…”

Section: Circuit Implementation 1 Digital Front-endmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Stereo Audio Delta-Sigma DAC with 40-kHz Bandwidth and 103-dB SNR

Yang¹,

Cho²,

Park³

et al. 2018

JSTS

View full text Add to dashboard Cite

show abstract

“…Recent techniques achieve this goal by using a mix of DAC elements with different weights, e.g., segmenting [1] or cascading [2]. Unlike 1b modulation, the multi-level DACs need mismatch shaping algorithms to compensate for the typical 0.1 to 1% on-die mismatch.…”

mentioning

confidence: 99%

“…Other proposed techniques [4] use modified digital algorithms with various trade-offs between mismatch shaping and the element transition rate. The pulse-width modulation (PWM) DAC method in [2] forces a fixed transition rate of the DAC elements, resulting in a significantly reduced sensitivity to ISI. However, this comes at the expense of a high clock rate which may not be available in the system.…”

mentioning

confidence: 99%

A 108dB-DR 120dB-THD and 0.5V<inf>rms</inf> output audio DAC with inter-symbol-interference-shaping algorithm in 45nm CMOS

Risbo

Hezar

Kelleci

et al. 2011

2011 IEEE International Solid-State Circuits Conference

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The current trend in high-performance audio DACs is to use fine-resolution quantization to reduce the out-of-band noise (OBN), reduce jitter sensitivity, and simplify analog filtering. Recent techniques achieve this goal by using a mix of DAC elements with different weights, e.g., segmenting [1] or cascading [2]. Unlike 1b modulation, the multi-level DACs need mismatch shaping algorithms to compensate for the typical 0.1 to 1% on-die mismatch. In addition to the element mismatch, dynamic error sources such as asymmetrical switching, clock skew, and parasitic memory are major hindrances to achieve distortion and dynamic range targets. The resulting dependence of present symbol error to the past symbol is referred to as inter-symbol-interference (ISI), and is a function of the switching activity of all the individual DAC elements. Unfortunately, the popular mismatch-shaping algorithms (e.g., rotation-DWA) are addressing only the static mismatch problem. They typically increase the switching activity thus amplify ISI errors. Furthermore, the error comes often in the form of spurious tones with signal-dependent frequency (FM modulation [3]) that ruins the lowamplitude performance (harmonics for a -60dB signal) which is critical for the perceived sound quality. A common remedy is to add a digital DC offset to shift the tones out of band. However, this merely moves the problematic amplitude region, and does not solve the problem. Moreover, ISI errors often limit the large signal THD as a result of a strong signal-dependent modulation of the element transition rate.One popular analog solution to reduce ISI errors is to use return-to-zero (RTZ) which eliminates the dependence on previous symbol. However, it results in increased current consumption, more high-frequency components, and higher sensitivity to circuit timing/jitter. Another analog solution [1] is to use a trackand-hold circuit to deglitch the waveform. However, such sampling circuits are sensitive to aliasing of high-frequency noise. Other proposed techniques [4] use modified digital algorithms with various trade-offs between mismatch shaping and the element transition rate. The pulse-width modulation (PWM) DAC method in [2] forces a fixed transition rate of the DAC elements, resulting in a significantly reduced sensitivity to ISI. However, this comes at the expense of a high clock rate which may not be available in the system.We propose a new digital algorithm that can shape element mismatch and ISI errors simultaneously. This method fully shapes ISI and the mismatch errors outside audio band and eliminates the need for layout critical and non-automated analog design methods that often require multiple design iterations and are hard to migrate over processes. This is enabled by using digital processing circuits that are simple and predictable with modern EDA tools and come at low cost in power and area using deep-submicron CMOS. In addition, the proposed solution works at regular DSM clock rate and does not require another PLL and clock management circuit.Th...

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Technology for the Next-Generation-Mobile User Experience

Delagi

2011

The Frontiers Collection

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A 110dB SNR and 0.5mW current-steering audio DAC implemented in 45nm CMOS

Cited by 10 publications

References 2 publications

A Stereo Audio Delta-Sigma DAC with 40-kHz Bandwidth and 103-dB SNR

A Stereo Audio Delta-Sigma DAC with 40-kHz Bandwidth and 103-dB SNR

A 108dB-DR 120dB-THD and 0.5V<inf>rms</inf> output audio DAC with inter-symbol-interference-shaping algorithm in 45nm CMOS

Technology for the Next-Generation-Mobile User Experience

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