A 110 nm CMOS process for fully-depleted pixel sensors

Abstract

This work presents a customized 110 nm CMOS process on high-resistivity substrate tailored for the production of fully-depleted pixel sensors. Starting from n-type substrates, customized surface implantations have been introduced to enable fast and efficient collection of the charge generated by ionizing particles or radiation. Double-sided processing has been used to define the backside electrode and the termination structures needed to bias the sensors at high voltage. A first run showing the feasibility of 300 µm-thick fully-depleted sensors was completed, and several test devices designed for the assessment of the process were fabricated together with a 24 × 24 pixels array with 50 µm pitch. The main technological challenges and the customization of the process are discussed, and electrical measurements on test devices demonstrating the functionality of the termination structures, the full depletion of the substrate and the fast charge collection are presented. K: Particle tracking detectors (Solid-state detectors); Photon detectors for UV, visible and IR photons (solid-state) (PIN diodes, APDs, Si-PMTs, G-APDs, CCDs, EBCCDs, EMCCDs, CMOS imagers, etc) 1Corresponding author.

A detector concept proposal for a circular e+e- collider

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Fully Depleted Monolithic Active Microstrip Sensors: TCAD Simulation Study of an Innovative Design Concept

“…The ARCADIA project and its precursor, SEED (Sensor with Embedded Electronics Development), designed an innovative sensor concept [ 37 , 38 ] based on a modified 110 nm CMOS process developed in collaboration with LFoundry and compatible with their standard 110 nm CMOS process. Up to 6 metal layers can be stacked on top of the sensor, for a total metal and insulator thickness of about 4–5 m. The ARCADIA collaboration is developing a scalable event-driven readout architecture to cover detection surfaces of O(cm ) while maintaining ultra-low power consumption.…”

“…The feasibility of this sensor concept and approach to Fully Depleted monolithic CMOS sensors was proven in the framework of the SEED project [ 37 , 38 ], and the design activities described in this article have as a starting point the experimental and simulation work performed in that project. The main constraint on the design was to reduce to the minimum the modifications to the foundry’s standard fabrication process, in order to guarantee easy portability to different commercial fabrication processes.…”

“…Three-dimensional simulations for the different cases were run and compared. Some simulation parameters were fine-tuned using characterization results from a previous set of test structures, produced in the framework of the SEED project [ 37 ].…”

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“…In order to provide a cost-effective solution, which could be easily portable to a more scaled process node, we focused on the development of FD-MAPS fabricated with a standard CMOS production process, with a backside junction obtained with low-temperature processing steps carried out after the completion of the entire front-side process [ 15 ]. In the first production run, both active pixel arrays with embedded electronics and passive test structures, designed to extract the device characteristic parameters and to characterize the sensor backside diodes, were included.…”