2009 IEEE Custom Integrated Circuits Conference 2009
DOI: 10.1109/cicc.2009.5280869
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A 10mW 9.7ENOB 80MSPS pipeline ADC in 65nm CMOS process without any special mask requirement and with single 1.3V supply

Abstract: This paper describes a power and area efficient pipeline ADC design. This ADC was designed in 65nm process without any special mask requirement and can work with supply voltage of 1.3V consuming 10mW providing 9.7 ENOB at 80MSPS while occupying less than 0.2 square millimeters. IEEE 2009 Custom Intergrated Circuits Conference (CICC)978-1-4244-4072-6/09/$25.00 ©2009 IEEE M-02-1

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“…Thus, we assume a 16-bit ADC. For a signal bandwidth W = 2 GHz, and f ADC = 500 KHz, and n = 16 bits, the power consumption of the ADC is 4.9 mW [18].…”
Section: Power Consumptionmentioning
confidence: 99%
“…Thus, we assume a 16-bit ADC. For a signal bandwidth W = 2 GHz, and f ADC = 500 KHz, and n = 16 bits, the power consumption of the ADC is 4.9 mW [18].…”
Section: Power Consumptionmentioning
confidence: 99%