A 10MHz signal bandwidth Cartesian-loop transmitter capable of off-chip PA linearization

Ishihara,; Hosoya,; Otaka,; Watanabe, Toru

doi:10.1109/isscc.2010.5434046

Cited by 4 publications

(1 citation statement)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Therefore, such solution tends to be more suitable for fully integrated transceiver systems rather than single-chip PA solutions. Other analog feedback methods, i.e., Cartesian and polar feedbacks, also require similar global feedback loop for real-time distortion cancellation [22] (Fig. 1.a).…”

Section: Introductionmentioning

confidence: 99%

A new wave of CMOS power amplifier innovations: Fusing digital and analog techniques with large signal RF operations

Kousai

Onizuka

et al. 2014

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

View full text Add to dashboard Cite

The RF power amplifier (PA) is typically the most power hungry and area consuming block in a wireless transceiver system. A viable RF PA solution should offer competitive power and area efficiency while maintaining high-performance large-signal RF operations. Fully integrated RF PA in CMOS has been an area of active research and development over the past years. Recently, there has been a surge of interest to leverage the mixed-mode, analog and digital, computational and signal processing capability in CMOS to radically enhance RF CMOS PA solutions and offer unique functionalities in parallel. This paper reviews several recently reported circuit design techniques of CMOS PAs. All of these techniques take advantage of computation and integration advantages of CMOS process and can potentially lead to competitive PA solutions compared to traditional III-V HBT PA solutions.Index Terms -CMOS power amplifiers, linearity improvement, impedance tuning, back-off efficiency, digital PA.

show abstract

Section: Introductionmentioning

confidence: 99%

A new wave of CMOS power amplifier innovations: Fusing digital and analog techniques with large signal RF operations

Kousai

Onizuka

et al. 2014

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

View full text Add to dashboard Cite

show abstract

A 28.3mW PA-closed loop for linearity and efficiency improvement integrated in a +27.1dBm WCDMA CMOS power amplifier

Kousai

Onizuka

Yamaguchi

et al. 2012

2012 IEEE International Solid-State Circuits Conference

View full text Add to dashboard Cite

28.8 A 21dBm-OP<inf>1dB</inf> 20.3%-Efficiency -131.8dBm/Hz-Noise X-Band Cartesian-Error-Feedback Transmitter with Fully Integrated Power Amplifier in 65nm CMOS

2019

2019 IEEE International Solid- State Circuits Conference - (ISSCC)

View full text Add to dashboard Cite

A 10MHz signal bandwidth Cartesian-loop transmitter capable of off-chip PA linearization

Cited by 4 publications

References 3 publications

A new wave of CMOS power amplifier innovations: Fusing digital and analog techniques with large signal RF operations

A new wave of CMOS power amplifier innovations: Fusing digital and analog techniques with large signal RF operations

A 28.3mW PA-closed loop for linearity and efficiency improvement integrated in a +27.1dBm WCDMA CMOS power amplifier

28.8 A 21dBm-OP<inf>1dB</inf> 20.3%-Efficiency -131.8dBm/Hz-Noise X-Band Cartesian-Error-Feedback Transmitter with Fully Integrated Power Amplifier in 65nm CMOS

Contact Info

Product

Resources

About

A 10MHz signal bandwidth Cartesian-loop transmitter capable of off-chip PA linearization

Cited by 4 publications

References 3 publications

A new wave of CMOS power amplifier innovations: Fusing digital and analog techniques with large signal RF operations

A new wave of CMOS power amplifier innovations: Fusing digital and analog techniques with large signal RF operations

A 28.3mW PA-closed loop for linearity and efficiency improvement integrated in a &#x002B;27.1dBm WCDMA CMOS power amplifier

28.8 A 21dBm-OP<inf>1dB</inf> 20.3%-Efficiency -131.8dBm/Hz-Noise X-Band Cartesian-Error-Feedback Transmitter with Fully Integrated Power Amplifier in 65nm CMOS

Contact Info

Product

Resources

About

A 28.3mW PA-closed loop for linearity and efficiency improvement integrated in a +27.1dBm WCDMA CMOS power amplifier