A 10b 100kS/s SAR ADC with charge recycling switching method

Chiang, K.H.; Chang, Soon-Jyh; Huang, Guan-Ying; Lin, Ying-Zu

doi:10.1109/asscc.2014.7008927

Cited by 4 publications

(1 citation statement)

References 6 publications

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“…Thus, reducing DAC switching power is recently a crucial topic to improve the overall power efficiency. Several low-power DAC switching techniques have been published including energy saving [1], charge recycling switching (CRS) [2], input range prediction (IRP) [3], charge average switching (CAS) [4], charge recycling with LSB-down [5], set-and-down [6], merge-and-split (MS) [7], bidirectional single-side (BSS) [8], Manuscript V cm -based [9], and one-side switching instead (OSSI)+higherbit switching instead (HBSI) [10] to reduce the switching energy by 69%, 71%, 74%, 75%, 77%, 81%, 83%, 86%, 88%, and 97%, respectively, compared with the conventional approach [6]. The switching power can also be reduced by detecting the input range and skipping unnecessary switching.…”

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confidence: 99%

A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching

Lee

Lin

Hsieh

2016

IEEE Trans. Circuits Syst. I

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This paper presents a low-voltage and powerefficient 10 bit successive-approximation register (SAR) analogto-digital converter (ADC). The input-range-adaptive (IRA) switching method is proposed to reduce the average switching power of capacitive digital-to-analog convertor (DAC) by 91% compared with the conventional approach. By utilizing the comparator as a voltage-to-time converter (VTC) with a timedomain quantizer, the implemented early-late (E/L) detection circuit, the input range is detected to eliminate the unnecessary DAC switching power efficiently. A prototype ADC chip is fabricated in 90 nm CMOS technology with an active area of 0.038 mm 2 . At 0.35-to-0.5 V supply voltage and 0.3-to-2 MS/s sampling rate with a Nyquist input, the ADC achieves a signalto-noise-plus-distortion ratio (SNDR) of 55.5 dB to 56.3 dB and a corresponding effective number of bits (ENOB) of 8.92 bit to 9.06 bit respectively with a power consumption of 0.3 µW to 2.5 µW and a resulting figure of merit (FoM) from 1.94 fJ/conversion-step to 2.32 fJ/conversion-step.Index Terms-Low power, low voltage, SAR ADC.

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