A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy

Sohn, Kiwon; Suh, Young-Joo; Son, Young‐Suk; Yim, Dae-Sik; Kim, Kang-Young; Bae, Dong-il; Kang, Ted; Lim, Hyun Suk; Jung, Soon‐Moon; Byun, Hyun-Geun; Jun, Young-Hyun; Kim, Kinam

doi:10.1109/isscc.2008.4523219

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State-of-the-art Techniques and Their Limitation1

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“…There are various assist techniques reported in the literature to enable ultra-low voltage SRAM. These assist techniques include boosted WL voltage [16,[82][83][84][85][86], under driven WL voltage [16], adjustment of cell-VDD (CVDD) [87][88][89][90][91][92], dual voltage supply scheme [16,88,93,94], negative bitline (BL) [90], and write-back (WB) schemes after read [17,89,95].…”

Section: State-of-the-art Techniques and Their Limitationmentioning

confidence: 99%