A 100 mm/sup 2/ 0.95 W single-chip MPEG2 MP@ML video encoder with a 128GOPS motion estimator and a multi-tasking RISC-type controller

Miyagoshi, E.; Araki, Takashi; Sayama, T.; Ohtani, Akira; Minemaru, T.; Okamoto, K.; Kodama, Hisashi; Morishige, T.; Watabe, Akihiko; Aoki, K.; Mitsumori, T.; Imanishi, H.; Jinbo, T.; Tanaka, Yoshinori; Taniyama, M.; Shingou, T.; Fukumoto, T.; Morimoto, H.; Aono, K.

doi:10.1109/isscc.1998.672363

Cited by 14 publications

(3 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The data-loading rate in the iterative-search block matching is approximately given by (10) In the adaptive iterative-search block matching, the data-loading rate is given by (11) where and express the data loading rate in the first iteration and that of the other iteration, respectively. and are approximately given by (12) and (13) respectively. In Table II, the data loading rate is also shown for the case that and .…”

Section: A Comparison Of Complexity and Memory Accessmentioning

confidence: 99%

See 1 more Smart Citation

Low-power motion vector estimation using iterative search block-matching methods and a high-speed non-destructive CMOS image sensor

Kawahito

Handoko

Tadokoro

et al. 2002

IEEE Trans. Circuits Syst. Video Technol.

View full text Add to dashboard Cite

In this paper, motion vector (MV) estimation methods with high-speed intermediate pictures for low-power video compression are proposed. The intermediate pictures are obtained by a special type of CMOS image sensor. An adaptive iterative-search block matching is proposed to obtain precise MVs of video-rate pictures from high-speed intermediate pictures with the reduced computational complexity. The sensor captures high-speed intermediate pictures without destructing signal charge and video-rate pictures with full signal accumulation time. The proposed active pixel sensor using bidirectional multiple charge transfer is useful for the nondestructive intermediate imaging with a reduced fixed pattern noise. The image sensor chip has been implemented by using 0.35-m CMOS technology. It operates with 3.3 V and captures 480 frames/s high-speed nondestructive intermediate pictures and 30 frame/s fully accumulated video-rate pictures. The proposed adaptive iterative-search block matching has a comparable precision to a full search block matching with reduction of computational complexity by a factor of about 1/13, on average. It also reduces the data-loading rate from the memory by a factor of about 1/4. Index Terms-Adaptive iterative-search block matching, bidirectional multiple charge transfer active pixel, high-speed nondestructive imaging, low-power video compression, motion vector estimation.

show abstract

Section: A Comparison Of Complexity and Memory Accessmentioning

confidence: 99%

“…Actually, MPEG2-encoder LSI chips at MP@ML (720 480 pixels) have been recently reported, for which the power dissipation is about 1 W with 0.25-m CMOS [13], [14].…”

Section: Power Dissipationmentioning

confidence: 99%

Low-power motion vector estimation using iterative search block-matching methods and a high-speed non-destructive CMOS image sensor

Kawahito

Handoko

Tadokoro

et al. 2002

IEEE Trans. Circuits Syst. Video Technol.

View full text Add to dashboard Cite

show abstract

“…Thus, it has been intensively studied from the standpoints of both hardware and software technologies. Single-chip MPEG-2 video encoder LSIs [2][3][4][5][6] have already been developed and widely used. Advanced and powerful microprocessor technology [7][8][9] has realized higher performance, and software developed based on these processors offers excellent performance for many multimedia applications in real time.…”

Section: Introductionmentioning

confidence: 99%

MPEG-2 real-time software CODEC for full-duplex transmission application over IP networks

Iwasaki¹,

Naganuma²,

Endo³

et al. 2005

Syst. Comp. Jpn.

View full text Add to dashboard Cite

SUMMARYThis paper proposes a real-time MPEG-2 software CODEC for full-duplex transmission applications, and evaluates its performance and usefulness. The CODEC consists of a high-speed encoder/decoder, an IP sender/receiver, and an error recovery controller. Each encoder/decoder is accelerated and optimized by exploiting fast algorithms and instruction-level parallelism. The IP sender/receiver combination achieves low delay owing to the direct translating of each elementary stream of video and audio into UDP/IP packets. The error recovery controller carries out simple but powerful error tolerance against packet loss over IP networks. This CODEC attains low delay of 99 ms (M = 1, N = 1) to 165 ms (M = 3, N = 3) including input, encoding, transmitting, decoding, and output delays, and maintains a normal frame rate of 30 fps (frames per second) and more than 20 fps even under a fairly heavy network load. It provides sufficiently good performance for use as a real-time full NTSC-size CODEC on a PC of at least 1.2-GHz CPU.

show abstract

A single-chip MPEG2 MP@ML video encoder LSI including wide search range motion estimation (H+/-288, V+/-96) and many functions for consumer use

Takashima

Ogura

Hiranaka

et al. 1998

IEEE Trans. Consumer Electron.

View full text Add to dashboard Cite

A 100 mm/sup 2/ 0.95 W single-chip MPEG2 MP@ML video encoder with a 128GOPS motion estimator and a multi-tasking RISC-type controller

Cited by 14 publications

References 4 publications

Low-power motion vector estimation using iterative search block-matching methods and a high-speed non-destructive CMOS image sensor

Low-power motion vector estimation using iterative search block-matching methods and a high-speed non-destructive CMOS image sensor

MPEG-2 real-time software CODEC for full-duplex transmission application over IP networks

A single-chip MPEG2 MP@ML video encoder LSI including wide search range motion estimation (H+/-288, V+/-96) and many functions for consumer use

Contact Info

Product

Resources

About