A 100 Mbps, LED Through-Wafer Optoelectronic Link for Multicomputer Interconnection Networks

May, P.; Lee, Myung‐Hee; Wilkinson, S.; Vendier, O.; Ho, Zhuang; Bond, Steven W.; Wills, D.S.; Brooke, M.A.; Jokerst, N.M.; Brown, April S.

doi:10.1006/jpdc.1996.1281

Cited by 8 publications

(6 citation statements)

References 21 publications

(22 reference statements)

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“…In this approach, only errors that are so severe that the CRC circuitry can not detect them are propagated through the network. The particular CRC that is used in this design is guaranteed to detect all one, two, and three bit errors in the flit, and any burst (sequential) errors up to seven bits in length [6].…”

Section: Flit-based Error Control and Wormhole Routingmentioning

confidence: 99%

“…Errors detected by the CRC circuitry can be eliminated (by retransmission) from the channel. The degradation of channel bandwidth due to retransmission is negligible for raw link BER values less than 10 [6]. The overhead of transmitting the CRC data accounts for a 20% loss of available channel bandwidth.…”

Section: Test Descriptionmentioning

confidence: 99%

“…CRC's have been extensively used in long haul telecommunication applications [8], [9] to validate data integrity when the possibility of a transmission error exists. We propose a new technique for applying CRC's to wormhole-routed multicomputer interconnection networks [3], [6]. Rather than providing end-to-end data validation on a low-error channel, we are employing CRC's in hop-byhop data validation to provide an acceptable effective BER using a lower power, higher bandwidth OE channel.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Improvement in bit-error rate for optoelectronic multicomputer interconnection networks using cyclic redundancy code error detection

May

Cross²,

Lopez-Lagunas³

et al. 1997

IEEE Photon. Technol. Lett.

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Abstract-This letter presents testing results of an integrated optoelectronic (OE) channel employing hop-by-hop error control circuitry based on cyclic redundancy codes (CRC) to improve the effective bit-error rate (BER). The use of OE interconnect in place of wires in multicomputer networks becomes more attractive as channel bandwidth and power efficiency are increased. But these improvements must be accomplished while maintaining an acceptable channel BER. Test results of an integrated OE channel incorporating CRC-based error control circuitry demonstrate a BER reduction of two orders of magnitude while incurring a 20% bandwidth overhead. This may lead to higher bandwidth and higher efficiency OE interconnects.

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Section: Flit-based Error Control and Wormhole Routingmentioning

confidence: 99%

Section: Test Descriptionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Improvement in bit-error rate for optoelectronic multicomputer interconnection networks using cyclic redundancy code error detection

May

Cross²,

Lopez-Lagunas³

et al. 1997

IEEE Photon. Technol. Lett.

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“…To address this issue, HiPER supports hop-by-hop flit-level retransmission of data that has encountered errors during transmission. May et al [13] discuss work in flit-level error control in multicomputer interconnection networks. The flit-level retransmission capability of the HiPER router places the responsibility of error control on the network itself, freeing the processor from the additional work required with an end-to-end retransmission scheme.…”

Section: Introductionmentioning

confidence: 99%

HiPER: a compact narrow channel router with hop-by-hop error correction

May

Bunchua

Wills

2002

IEEE Trans. Parallel Distrib. Syst.

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Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communicate at significantly higher speeds while operating more efficiently to meet system size, weight, power, and energy requirements. As high-performance parallel computing architectures make their way into portable systems, compact, efficient, and error-tolerant computing and communication mechanisms will be required. This paper presents the High-Performance Efficient Router (HiPER), an efficient multidimensional router supporting high-throughput errorcorrected communication channels. HiPER is a proof-of-concept vehicle for efficient implementations of routing, switching, and error control mechanisms. It combines mad postman (bit-pipelined) switching with dimension-order routing, producing a low-latency routing router that is less sensitive to message distance than a word parallel crossbar router. To maintain robust communication as link speeds increase and link power budgets decrease, HiPER employs flit-level hop-by-hop retransmission of erroneous flits, which provides builtin error control at the network level. Data presented on the implemented bit serial version of HiPER offer insight into future router designs with channel sizes between bit-serial and word-wide.

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“…Although a number of studies have investigated the technical feasibility of through-wafer optical links [6], [24], [35], no studies have explored what network topologies best exploit this technology from a packaging standpoint. An obvious evolutionary strategy is to use through-wafer signaling to enhance the physical implementation of an existing network topology.…”

Section: Introductionmentioning

confidence: 99%

The offset cube: a three-dimensional multicomputer network topology using through-wafer optics

Lacy

Cruz-Rivera

Wills

1998

IEEE Trans. Parallel Distrib. Syst.

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Three-dimensional packaging technologies are critical for enabling ultra-compact, massively parallel processors (MPPs) for embedded applications. Through-wafer optical interconnect has been proposed as a useful technology for building ultra-compact MPPs since it provides a simplified mechanism for interconnecting stacked multichip substrates. This paper presents the offset cube, a new network topology designed to exploit the packaging benefits of through-wafer optical interconnect in ultra-compact MPP systems. We validate the offset cube's topological efficiency by developing deadlock-free adaptive routing protocols with modest virtual channel requirements (only two virtual channels per link needed for full adaptivity). A preliminary analysis of router complexity suggests these protocols can be efficiently implemented in hardware. We also present a 3D mesh embedding for the offset cube. Network simulations show the offset cube performs comparably to a bidirectional 3D mesh of equal size under uniform, hot-spot, and trace-driven traffic loads. While the offset cube is not proposed as a general replacement for the mesh topology, it leverages the benefits of through-wafer optical interconnect more effectively than a mesh by completely eliminating chip-to-chip wires for data signals. Hence, the offset cube is an effective topology for interconnecting ultra-compact MCM-level MPP systems.

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A 100 Mbps, LED Through-Wafer Optoelectronic Link for Multicomputer Interconnection Networks

Cited by 8 publications

References 21 publications

Improvement in bit-error rate for optoelectronic multicomputer interconnection networks using cyclic redundancy code error detection

Improvement in bit-error rate for optoelectronic multicomputer interconnection networks using cyclic redundancy code error detection

HiPER: a compact narrow channel router with hop-by-hop error correction

The offset cube: a three-dimensional multicomputer network topology using through-wafer optics

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