1991
DOI: 10.1109/4.104187
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A 10-GHz 8-b multiplexer/demultiplexer chip set for the SONET STS-192 system

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Cited by 26 publications
(3 citation statements)
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“…To satisfy this condition, the clock signal for the selector should be delayed by from that for the D-FF's. In the conventional MUX/DEMUX [6]- [8], such phase differences are produced by inverter chains. The delay time of inverter chains is, however, significantly affected by threshold voltage deviation of FET's at a low supply voltage.…”
Section: Introductionmentioning
confidence: 99%
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“…To satisfy this condition, the clock signal for the selector should be delayed by from that for the D-FF's. In the conventional MUX/DEMUX [6]- [8], such phase differences are produced by inverter chains. The delay time of inverter chains is, however, significantly affected by threshold voltage deviation of FET's at a low supply voltage.…”
Section: Introductionmentioning
confidence: 99%
“…However, this architecture requires precisely controlled timing of the internal signal for stable operation. To ensure sufficient timing margin, a master-slave D-FF (MS-D-FF) consisting of two latches and a phase-shifting D-FF (PS-D-FF) consisting of three latches are employed in the 2:1 MUX's and the 1:2 DEMUX's [6], [7]. Latches are also introduced in the timing control block as described in the next section.…”
Section: Introductionmentioning
confidence: 99%
“…This IC was fabricated using a 0.5 km WNx-gate GaAs MESFET with BPLDD structure [7] as shown in Fig.5.…”
Section: Fig4 Microphotograph Of the Qpsk Modulator Icmentioning
confidence: 99%