A 10 Gb/s Equalizer in 0.18m CMOS Technology for High-speed SerDes

Zhang, Mingke; Hu, Qingsheng

doi:10.14257/ijca.2014.7.11.28

IJCA

2014

DOI: 10.14257/ijca.2014.7.11.28

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A 10 Gb/s Equalizer in 0.18m CMOS Technology for High-speed SerDes

Mingke Zhang¹,

Qingsheng Hu²

Abstract: A 10 Gb/s equalizer consisting of analog equalizer and two-tap half-rate decision feedback equalizer (DFE)

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A 10 Gb/s Equalizer in 0.18m CMOS Technology for High-speed SerDes

Abstract: A 10 Gb/s equalizer consisting of analog equalizer and two-tap half-rate decision feedback equalizer (DFE)

Cited by 0 publications

References 5 publications

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