A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS

Abstract

A compact and power-efficient serial I/O targeting dense silicon carrier interconnects is reported. Based on expected channel characteristics, the proposed I/O features low-impedance transmitter termination, high-impedance receiver termination, and a receiver with modified DFE with IIR filter feedback (DFE-IIR). The DFE-IIR receiver uses a single additional IIR filter feedback tap to compensate many postcursors without paying the power and area penalty that would be incurred with a conventional high tap-count DFE. Equalization capabilities of the compact I/O at 10 Gb/s are demonstrated over various channels including conventional chip-to-chip and backplane links with half-baud losses of up to 27 dB. Finally, a transmitter-receiver pair operating over a 40-mm on-chip emulated silicon carrier channel was demonstrated to 8.9 Gb/s, at a link power efficiency of 1.9 mW/Gb/s. Index Terms-Backplane channel communication, chip-to-chip communication, compact I/O, continuous-time IIR filter, decision feedback equalizer, serial link, silicon carrier links.

A Channel Model of Scaled RC-dominant Wires for High-Speed Wireline Transceiver Design

“…In general, wire pitches shrink faster than modules allowing more wires between modules. This trend of interconnect scaling is reported in many articles [2][3][4][6][7][8][9][10][11][12]. Knickerbocker greatly scaled length and density of interconnects by densely populating chip dies on a silicon substrate package called "silicon carrier" instead of on a PCB [6].…”

“…(10)-(13) to understand two example signaling and termination strategies [7,8,11,12]. We can explain the transmitter termination strategy used in [7] by using Eqs. (10)- (13).…”

“…This SiP technology leveraged a good thermal expansion match between dies and a package medium, and used back-end-of-line (BEOL) and through-silicon-vias (TSV) to reduce wire pitch and to increase input/output (I/O) density. Kim and Liu discussed high-speed wireline transceiver design for silicon carrier packages [7,8]. Kang demonstrated a 3-D stacked DRAM chip in a single package using TSV technology [9].…”

Design Techniques for High-Speed I/Os: Challenges and Opportunities

“…It is also used solely for channels with negligible reflection and crosstalk [53,54]. Because the received symbol is severely attenuated, input offset voltage compensation is typically required in CTLE [55,56]. Unlike CTLE, nonlinear post-equalization removes post-cursors by subtracting estimated post-cursors directly from data symbols prior to slicing.…”

A 10-Gb/s low-power adaptive continuous-time linear equalizer using asynchronous under-sampling histogram

“…A tunable passive filter with power comparison adaptation can achieve low-power consumption but further improvement is required in input impedance matching and output swing levels [1]. Decision feedback equalizers (DFEs) have been used in low-power transceivers [2]. For DFEs, however, clock recovery and distribution circuits are required, making it difficult to use these equalizers if received data eyes are initially closed.…”