A 10-bit 2GHz Current-Steering CMOS D/A Converter

Ling, Yuan Yuan; Ni, Weining; Yin, Shi; Dai, Fa Foster

doi:10.1109/iscas.2007.377991

Cited by 4 publications

(2 citation statements)

References 8 publications

(8 reference statements)

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“…The DNL error and switching dynamic errors are substantially improved here at a cost of increased complexity, area and power consumption. However, to get the advantages of both implementations, most current-steering DACs are implemented using a segmented architecture [1][2][3]. Different structures can be derived from these basic architectures and some recent papers have used the idea of connection of subDACs in parallel to regroup the current cells enabling flexibility and smartness for the new architecture without manifesting any evidence of saved area and power efficiency [4], or to reduce the area occupied by the converter without resolving the mismatch problem between subDACs [5,6].…”

Section: Introductionmentioning

confidence: 99%

A 12-bit 0.35 μm CMOS area optimized current-steering hybrid DAC

Myderrizi

Zeki

2010

Analog Integr Circ Sig Process

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In this paper a 12-bit current-steering hybrid DAC is implemented using AMS 0.35 lm CMOS process technology. The architecture and design methodology used for the implementation of the DAC offer advantages like design speed up, easiness in design and a small active area. The proposed hybrid DAC consists of four 3-bit parallel matched current-steering subDACs and resistive networks that properly weight the current output of each subDAC to obtain the overall voltage-mode output of the 12-bit hybrid DAC. The performance of the hybrid DAC is validated through static and dynamic performance metrics. Simulations indicate that the DAC has an accuracy of 12-bit and a SFDR higher than 66 dB in whole Nyquist frequency band. The simulated INL is better than 1 LSB, while simulated DNL is better than 0.25 LSB. At an update rate of 250 MS/s the SFDR for signals up to 10 MHz is higher than 66 dB. The Figure of Merit (FoM) of the implemented hybrid DAC is better than recently presented DACs with 12-bit resolutions and implemented using various process technologies. The proposed hybrid DAC supporting high update rates with good dynamic performance can be used as an alternative in various applications in industry including video, digital TV, cable modems etc.

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Section: Introductionmentioning

confidence: 99%

A 12-bit 0.35 μm CMOS area optimized current-steering hybrid DAC

Myderrizi

Zeki

2010

Analog Integr Circ Sig Process

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“…Current steering converters, in general, have as main advantages a small silicon area and a high update rate. Most reported current steering converters [5]- [8] use the segmented architecture, where a good balance between performance specifications versus power, area and complexity is found.…”

Section: Introductionmentioning

confidence: 99%

A CMOS-only R-2R ladder D/A converter for image sensor applications

Domingues

Braga

Mesquita

2009

2009 3rd International Conference on Signals, Circuits and Systems (SCS)

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This paper presents a monotonic CMOS-only R-2R ladder D/A converter to be used in a single-slope A/D converter for image sensor applications. It employs complementary switches with dummy transistors in the ladder to reduce the glitch energy of the output. This does not affect the monotonicity of the ladder and adds less than 0.5% to the total mismatch variations. The estimate of the mismatch variations results in 99.5% of probability for monotonic behavior of the fabricated chips. The complete D/A converter was implemented in a standard 0.35 µm CMOS process and occupies an area of only 0.03 mm 2 . Post-layout simulations showed that the DNL graph does not exceed the range of ± 1 LSB, which indicates a monotonic behavior of the D/A converter. The average power consumption for the conversion of a full digital cycle is 0.55 mW.

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A 1-V 10-bit 2GSample/s D/A converter based on precision current reference in 90-nm CMOS

Cheng

Wang

Huang

2008

2008 15th IEEE International Conference on Electronics, Circuits and Systems

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This paper describes a 2GS/s 10bit DAC with a supply voltage lower to 1 volt. It has been realized in a 90-nm 1P9M CMOS technology. A novel high precision active cascode mirror circuit is presented. Provided the headroom is not affected, operating the current source in the triode region, the precision of the current source array can be obtained. In addition, the demand of low analog/digital supply voltage and the influence of MOS short-channel effect can be overcome. The INL is between +0.12 and -0.14 LSB, and the DNL is between +0.23 and -0.35 LSB. When the DAC operates at an input signal frequency of 10MHz, a SFDR of 65.1dB can be achieved. Moreover, a SFDR of 54.4dB can be gained when the DAC operates at 982.2MHz. The power consumption of the proposed design is approximately 79mW. The chip area is about 1mm × 1mm.

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A 10-bit 2GHz Current-Steering CMOS D/A Converter

Cited by 4 publications

References 8 publications

A 12-bit 0.35 μm CMOS area optimized current-steering hybrid DAC

A 12-bit 0.35 μm CMOS area optimized current-steering hybrid DAC

A CMOS-only R-2R ladder D/A converter for image sensor applications

A 1-V 10-bit 2GSample/s D/A converter based on precision current reference in 90-nm CMOS

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