2021
DOI: 10.1016/j.mejo.2021.105109
|View full text |Cite
|
Sign up to set email alerts
|

A 10-bit 20-MS/s SAR DAC achieving 57.9-dB SNDR using insensitive geometry DAC array

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
0
0

Year Published

2023
2023
2023
2023

Publication Types

Select...
1

Relationship

0
1

Authors

Journals

citations
Cited by 1 publication
(1 citation statement)
references
References 23 publications
0
0
0
Order By: Relevance
“…In addition, the mismatch between capacitors is a new problem. Conventionally, the mismatch of each capacitor in DAC array becomes smaller with a larger unit capacitance or an advanced process, but it increases the cost [11] [12]. So, this traditional structure is not suitable for the SAR ADC designed in this paper.…”
Section: Capacitor Array Designmentioning
confidence: 99%
“…In addition, the mismatch between capacitors is a new problem. Conventionally, the mismatch of each capacitor in DAC array becomes smaller with a larger unit capacitance or an advanced process, but it increases the cost [11] [12]. So, this traditional structure is not suitable for the SAR ADC designed in this paper.…”
Section: Capacitor Array Designmentioning
confidence: 99%