A 10‐bit 13.3 µW single‐slope analog‐to‐digital converter with auto‐zero power‐down technique
Youngwoo Lee,
Suhwan Kim,
Jaehoon Jun
Abstract:This letter presents a low‐power single‐slope analog‐to‐digital converter (ADC) for column‐parallel architectures. A simple and effective design technique is proposed to solve the input‐dependent power consumption problem of the conventional single‐slope ADCs. A decision‐feedback loop is implemented in the second stage of the comparator. Based on the negative‐feedback path, which is activated after the signal decision of the comparator, the input‐dependent dynamic current path in the amplifier is disabled. Fur… Show more
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