A 10-Bit 10-Ms/S 5.72 nW Mixed SAR Logic for ADC Used in Wireless Sensor Node

Marathe, Dipak S.; Khot, Uday Pandit

doi:10.1109/icnte44896.2019.8946000

Cited by 2 publications

(3 citation statements)

References 11 publications

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“…The duty cycle has a direct relationship with the average power consumed by the circuit shown in Eq. (6). A comparator uses a clock signal, i.e., variation in the period of a clock varies the power.…”

Section: Optimum Duty Cyclementioning

confidence: 99%

“…A mixed mode architecture uses a global clock net to partitioning the design. Each partitioned part exchanges data asynchronously using handshake signals [6]. The designing of synchronous and asynchronous 10-bit SAR is carried out using CMOS 180…”

Section: Mixed Mode Sar Logicmentioning

confidence: 99%

“…9. A digital logic input coming from mixed mode SAR logic [6] drives a thermometer DAC switching matrix. The transient simulation of 10-bit current mode DAC is shown in Fig.…”

Section: Current Mode Dacmentioning

confidence: 99%

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A 1-V 10-bit 16.83-fJ/Conversion-step Mixed Current Mode SAR ADC for WSN

Marathe¹,

Khot²

2019

IJIGSP

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This paper proposes a 10-bit mixed current mode low power SAR ADC for sensor node application. The different entities of a successive approximation register (SAR) analog-to-digital converter (ADC) circuit has a hybrid or mixed mode approach i.e.,voltage mode regenerative comparator; mixed SAR logic; and current mode digital-to-analog converter (DAC). The performance limitation of speed and the kick-back noise of a dynamic comparator is resolved using duty cycle controlled regenerative comparator. A mixed mode logic of a SAR is partitioning the design into synchronous ring counter and asynchronous output register. The data shifting of a ring counter is with the common clock tick while the output register exchanged it asynchronously using handshake signals, resulting in a low power SAR. The current mode switching function in a DAC to reduce asynchronous switching effect resulting in a low energy conversion per step. In overall, the proposed mixed SAR ADC consumes a 41.6 W  power and achieves an SFDR 69.3 dB at 10 MS/sec and 1 V supply voltage. It is designed and simulated in the 0.18  m TSMC CMOS process. Index Terms-Successive approximation register (SAR), mixed-mode, current-mode, regenerative-comparator, analog-to-digital-converter (ADC), digital-to-analog converter (DAC).

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Section: Optimum Duty Cyclementioning

confidence: 99%

Section: Mixed Mode Sar Logicmentioning

confidence: 99%

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A 1-V 10-bit 16.83-fJ/Conversion-step Mixed Current Mode SAR ADC for WSN

Marathe¹,

Khot²

2019

IJIGSP

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A 14-bit High Speed 125MS/s Low Power SAR ADC using Dual Split Capacitor DAC Architecture in 90nm CMOS Technology

Shetty

Nagabushanam

Prasad

2021

International Journal of Circuits, Systems and Signal Processing

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The proposed work presents a High speed 14-bit 125MS/s successive-approximation-register asynchronous analog-to-digital-converter (SAR-ADC). A novel-based Dual-Split-Array-Three-Section (DSATS) capacitor DAC (DSATS-CDAC) is employed to increase the linearity and energy efficiency of the digital-to-analog converter (DAC), additional advantage of this work is that, the area is reduced by 59.76% of conventional design. The proposed switching technique of the (DSATS-CDAC) consumes less switching energy. Additionally, bootstrap switching is employed to ensure improved linearity and reduced power consumption.in order to enhance the speed of operation and increase the precision a preamplifier latch based comparator is implemented with the delay of 250ps. The proposed SAR-ADC prototype is implemented in a 90nm CMOS process and consumes a power of 42.8mW at 1V operating supply. The proposed design achieves a figure of merit (FOM) of 37.43 fJ/conversion-step, signal-to-noise-ratio (SNR) of 81 dB, and an effective-number-of-bits (ENOB) of 13.16 bits with a sampling rate of 125MS/s.

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A 10-Bit 10-Ms/S 5.72 nW Mixed SAR Logic for ADC Used in Wireless Sensor Node

Cited by 2 publications

References 11 publications

A 1-V 10-bit 16.83-fJ/Conversion-step Mixed Current Mode SAR ADC for WSN

A 1-V 10-bit 16.83-fJ/Conversion-step Mixed Current Mode SAR ADC for WSN

A 14-bit High Speed 125MS/s Low Power SAR ADC using Dual Split Capacitor DAC Architecture in 90nm CMOS Technology

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