A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter

Bosch, A. Van den; Borremans, M.; Steyaert, Michiel; Sansen, Willy

doi:10.1109/4.910469

Cited by 315 publications

(23 citation statements)

References 11 publications

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“…It has the benefit of not necessarily requiring an output buffer for high performance. It directs all its current to the output, which means high efficiency can be achieved [74,2,29,28]. A simplified block diagram of a binary-weighted current-steering DAC with digital input signal as D…”

Section: Current-steering Dac For High-speed Operationmentioning

confidence: 99%

Studies on Selected Topics in Radio Frequency Digital-to-Analog Converters

Sadeghifar

2019

Linköping Studies in Science and Technology. Dissertations

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The network latency in fifth generation mobile technology (5G) will be around one millisecond which is much lower than in 4G technology. This significantly faster response time together with higher information capacity and ultra-reliable communication in 5G technology will pave the way for future innovations in a smart and connected society. This new 5G network should be built on a reasonable wireless infrastructure and 5G radio base stations that can be vastly deployed. That is, while the electrical specification of a radio base station in 5G should be met in order to have the network functioning, the size, weight and power consumption of the radio system should be optimized to be able to commercially deploy these radios in a huge network. Last but not least I would like to especially thank my soulmate and my love Hoda. Without all your help, your devotion and patience, I would not be able to complete this work. Therefore, I dedicate this work to you.

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Section: Current-steering Dac For High-speed Operationmentioning

confidence: 99%

Studies on Selected Topics in Radio Frequency Digital-to-Analog Converters

Sadeghifar

2019

Linköping Studies in Science and Technology. Dissertations

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“…The Current-steering DAC is a good candidate for high-speed DAC applications because it can drive low impedance directly with good linearity, and without needing high-speed buffers. There are three different architectures used to implement the switched current source array, they are binary, unary, and segmented [1]. The binary-weighted architecture is the simplest design with low digital power and small area, and it achieves compatible static and dynamic performance compared with other structures [2][3].…”

Section: Introductionmentioning

confidence: 99%

A 10-bit 250MS/s low-glitch binary-weighted digital-to-analog converter

Chou

Chen

Hung

2014

2014 27th IEEE International System-on-Chip Conference (SOCC)

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This paper presents a 10-bit all binary-weighted current-steering digital-to-analog converter (DAC) with low-glitch and low-power properties. Instead of using large input buffers, the proposed design uses variable-delay buffers to compensate for the delay difference among different bits, and to reduce high glitch energy from 132pVs to 1.36pVs during major code transition. The spurious free dynamic range (SFDR) has been improved over 10dB compared to the conventional DAC without variable-delay buffers. This chip was implemented in a standard 0.18um CMOS process, and dissipates 19mW from a single 1.8V power supply.

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“…Conventional techniques to design 12-bit current-steering DACs were heavily based upon segmented structure which combined binary weighted DAC and thermometer decoder DAC for high-speed and high-resolution. However, segmented structure suffers from a large power consumption, complexity and size of converter due to additional decoding logic circuits [2][3][4][5][6][7][8][9][10][11][12][13][14]. In this paper, a low power DAC with pseudosegmentation for WLAN is proposed.…”

Section: Introductionmentioning

confidence: 99%

A low-power 12-bit 80MHz CMOS DAC using pseudo-segmentation

Joo

Kim

Yoon

2008

Proceedings of the 18th ACM Great Lakes Symposium on VLSI

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This paper describes the design of a low-power 12-bit CMOS DAC using pseudo-segmentation technique. Pseudo-segmentation used in binary decoder consists of simple parallel buffers for low power because of simpler configuration than that of thermometer decoder. The measurement results show the conversion rate of 80MHz and the power dissipation of 46.8mW at single supply voltage of 1.8V. ±1.6LSB / ±1.2LSB of INL and DNL have been measured for linearity. The ENOB and SFDR of the proposed 12bit DAC were measured to be 10.67 bit and 66.01dBc @ Fs=80MHz, Fin=1MHz, respectively. Glitch energy was measured to be 49 pV·s.

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A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter

Cited by 315 publications

References 11 publications

Studies on Selected Topics in Radio Frequency Digital-to-Analog Converters

Studies on Selected Topics in Radio Frequency Digital-to-Analog Converters

A 10-bit 250MS/s low-glitch binary-weighted digital-to-analog converter

A low-power 12-bit 80MHz CMOS DAC using pseudo-segmentation

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