A 10-b 40-MHz 0.8- mu m CMOS current-output D/A converter

Bastiaansen, Corné; Groeneveld, D.W.J.; Schouwenaars, H.J.; Termeer, H.A.H.

doi:10.1109/4.92010

Cited by 79 publications

(9 citation statements)

References 5 publications

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“…The signal-scaling action in current-steering DACs is obtained by means of active-device scaling and, thus, no need for passive components appears, avoiding the use of linear capacitors (which, in turn, require one extra polysilicon layer process step). The current-steering DAC, being in fact a switched current mirror, achieves high-frequency operation because of the inherent reduction of voltage swings, thus minimising sensitivities to parasitic capacitances [51].…”

Section: Current-steering Mixed-signal Multipliermentioning

confidence: 99%

Mixed-Signal Neuro-Fuzzy Processor Implementations: Sequential Architectures and Circuit-Level Description

Madrenas¹,

Alarcón²

2002

Series in Machine Perception and Artificial Intelligence

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Mixed-signal VLSI design provides a tradeoff between the fast and compact but fixed analog implementations of neuro/fuzzy feedforward algorithms and the programmable but area and power consuming digital counterparts. In this chapter, a sequentiality study of such systems is performed. Basic blocks for sequential mixed-signal neural and fuzzy computing are proposed, and two sequential example processors are described. Feedback from the designed processors and subcircuits allowed considering the technology constraints for analysis and extension to different sequentiality degrees. IntroductionIn this chapter, we introduce architecture analysis and guidelines to develop sequential analog processing circuits. By means of switched techniques and analog memory elements, analog sequential processing circuits can be designed. These techniques are applied to the development of mixed-signal neural and fuzzy processors. For this purpose, the characteristics, constraints and properties of analog circuits, that are very different from their digital counterparts, have to be taken into account. At the architectural level, starting from sequential architectures of neural and fuzzy models, a performance analysis in terms of area and speed as a function of the sequentiality -or parallelism-degree is developed.Efficiency in terms of silicon area occupancy versus computation performance (speed) is fundamental in autonomous intelligent systems. For 93 Neural Networks and Systolic Array Design Downloaded from www.worldscientific.com by MONASH UNIVERSITY on 04/23/17. For personal use only.

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Section: Current-steering Mixed-signal Multipliermentioning

confidence: 99%

Mixed-Signal Neuro-Fuzzy Processor Implementations: Sequential Architectures and Circuit-Level Description

Madrenas¹,

Alarcón²

2002

Series in Machine Perception and Artificial Intelligence

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“…10). The combiner acts as digital to analog converter by switching the transistors with binary inputs and summing the currents across the load [10]. The binary coded transistors' sizing incorporate weight to bits from LSBs to MSBs.…”

Section: Vlsi Implementation Of Idm Adcmentioning

confidence: 99%

A low power 6-bit A/D converter achieving 10-bit resolution for MEMS sensor interface using time-interleaved delta modulation

De¹,

Kal

2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

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This paper describes time-interleaved delta ADC as a digital interface for low frequency MEMS sensor signal. The design is presented as a simple low power solution for A/D conversion in comparison to popular sigma-delta converters. Conventional delta modulator is modified with insertion of an array of comparators and a coder i.e. an up/down counter. Time interleaving is done within the array to operate the sensitive analog part in slower speed while maintaining a higher oversampling ratio of the converter. The up/down counter acts as low-pass filter in the delta modulation loop and by resetting it in proper interval decimationcan also be performed. Simulation of the test structure for the 6-bit ADC in 0.18µm CMOS process shows output SNR of 60dB, with INL and DNLs less than 0.5 LSB. The output SNR is equivalent to 10-bit of resolution. To obtain such resolution with only 6-bit output the total power the design consumes from a single 1.8 V supply is only 2.3mW. The die area of the ADC is only 0.8mm×0.6mm.

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“…In small parts of the wafer, a transistor parameter can be approximated by linear dependence with the position [4]. Figure 7 shows the layout of the circuit.…”

Section: Tv Errors Due To Mismatchmentioning

confidence: 99%

A Floating-Point A/D Converter for Smart Sensors

Mahmoud

Wolffenbuttel

1992

ESSCIRC '92: Eighteenth European Solid-State Circuits Conference

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A binary scaled programmable current source has been designed for use in a non¬ linear A/D converter for smart sensors applications. The non-linear conversion is achieved by using accurate binary-weighted current sources with emitter scaling and analog current switches. The A/D converter implements two programmable current sources, the first is used to determine the exponent, while the second is used to determine the mantissa in a floating point representation number. The current source and the required electronics are implemented using a bipolar process in silicon which makes it compatible with silicon sensors. A special layout has been implemented in the design to compensate for mismatch gradients over the chip.

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A 10-b 40-MHz 0.8- mu m CMOS current-output D/A converter

Cited by 79 publications

References 5 publications

Mixed-Signal Neuro-Fuzzy Processor Implementations: Sequential Architectures and Circuit-Level Description

Mixed-Signal Neuro-Fuzzy Processor Implementations: Sequential Architectures and Circuit-Level Description

A low power 6-bit A/D converter achieving 10-bit resolution for MEMS sensor interface using time-interleaved delta modulation

A Floating-Point A/D Converter for Smart Sensors

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