A 10 b 100 Ms/s pipelined subranging BiCMOS ADC

Sone, K.; Nakadai, N.; Nishida, Y.; Ishida, M.; Sekine, Y.; Yotsuyanagi, M.

doi:10.1109/isscc.1993.280081

Cited by 6 publications

(1 citation statement)

References 3 publications

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“…In order to overcome these problems, variations on the flash architecture have been developed which use relatively few comparators yet retain good speed. Examples capable of Gs/s rates are the folded-flash [12]- [14]; and pipelined [15], [16] architectures.…”

Section: High-performance Adc Architecturesmentioning

confidence: 99%

Analog-to-digital converter survey and analysis

Walden

1999

IEEE J. Select. Areas Commun.

1,817

959

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Abstract-Analog-to-digital converters (ADC's) are ubiquitous, critical components of software radio and other signal processing systems. This paper surveys the state-of-the-art of ADC's, including experimental converters and commercially available parts. The distribution of resolution versus sampling rate provides insight into ADC performance limitations. At sampling rates below 2 million samples per second (Ms/s), resolution appears to be limited by thermal noise. At sampling rates ranging from 2 Ms/s to 4 giga samples per second (Gs/s), resolution falls off by 1 bit for every doubling of the sampling rate. This behavior may be attributed to uncertainty in the sampling instant due to aperture jitter. For ADC's operating at multi-Gs/s rates, the speed of the device technology is also a limiting factor due to comparator ambiguity. Many ADC architectures and integrated circuit technologies have been proposed and implemented to push back these limits. The recent trend toward single-chip ADC's brings lower power dissipation. However, technological progress as measured by the product of the ADC resolution (bits) times the sampling rate is slow. Average improvement is only 1.5 bits for any given sampling frequency over the last six-eight years.Index Terms-Analog-to-digital converters, aperture jitter, comparator ambiguity, input-referred noise, signal-to-noise ratio, spurious-free dynamic range.

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Section: High-performance Adc Architecturesmentioning

confidence: 99%

Analog-to-digital converter survey and analysis

Walden

1999

IEEE J. Select. Areas Commun.

1,817

959

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A 10-b 50 MS/s 500-mW A/D converter using a differential-voltage subconverter

Miki

Kouno

Kumamoto

et al. 1994

IEEE J. Solid-State Circuits

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ADC and DSP challenges in the development of software radio base stations

1999

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The need for software-defined radios raiscs a number of tcchnical challcngcs, which play a significant role in the development of third-generation personal communications systems (PCS). Some of the most important tcchnical challenges deal with analog-to-digital conversion and digital signal processing tcchnologics, which, in many cascs, cannot provide the advanced hardware ncedcd to support the dcmanding PCS tclccommunications services. In this articlc, we discuss thcsc two tcchnical challenges, focusing primarily on hase station radio systcms. We first idcntify the most important requirements for ADC and DSP technologies, and we then extcnsively discuss and/or propose enabling schemes that could relax thcsc rcquircmcnts and aid thc implcmcntation of software radio base stations.Furthermore, wc discuss new structurcs thill can support the dcvclopincnt of physically distrihutcd base stations.

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A 10 b 100 Ms/s pipelined subranging BiCMOS ADC

Abstract: While 10b 75Mds ADCs for HDTV studio-equipment using a bipolar process and a subranging architecture or a flash architecture using interpolation techniques have been reported, these ADCs dissipate more than 2W [1,21.

Cited by 6 publications

References 3 publications

Analog-to-digital converter survey and analysis

Analog-to-digital converter survey and analysis

A 10-b 50 MS/s 500-mW A/D converter using a differential-voltage subconverter

ADC and DSP challenges in the development of software radio base stations

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