A 10 b, 100 Ms/s pipelined A/D converter

Abstract

Power dissipation in high-speed, wide-dynamic-range AD converters may be reduced by use of an advanced IC process, and by employing subranging A/D conversion architectures. The ADC described here is fabricated in an oxide-isolated bipolar process offering 4GHz npn transistors at the low bias currents used throughout. The two-step subranging architecture consists of a 4b coarse quantizer, followed by a 7b fine quantizer (Figure 1). 10b linearity is required in only three circuits: (a) the input track and hold (T/H 1) that must sample the input with the full linearity, even under the largest admissible input slew rate; (b) the reconstruction DAC that must correct for nonlinearity in the (fast) 4b coarse quantizer; (c) the input ports ofthe subtraction circuit that must correctly form the residue between the input sample and an analog reconstruction of the 4b coarse-quantized word.The ADC uses a single clock of 50% duty cycle to activate each stage once every half cycle. A I n s delay is inserted between the clock used to sample the input and the strobe t o the latches in the coarse quantizer. The intermediate T/H appears after the residue calculation to avoid unnecessary level shifts, and need only be 7b linear. The maximum clock rate for the A/D is limited by the combined settling time through the coarse quantizer, DAC, and residue amplifier. All circuits operate at power supplies of 0 and -5V, except the two T/H circuits where +5V is used for pullup biasing.A fully-differential flash quantizer encodes the input to 4b. The total drop of512mVacross the ladder defines the input full scale. Voltage bowing due to the base current flowing through the ladder resistors is nulled in this differential scheme at the one critical comparator poised at the trip point.To reduce comparator count, the largest source of power dissipation in the 7b fine quantizer, an analog subranging technique is used ( Figure 2) [1,21. Folding amplifiers, analog circuits with a multi-cycle periodic input-output characteristic, map a full-scale excursion ofthe input into a sub-scale that is then quantized. Encoding relative to the full scale is obtained by combining this sub-scale code with a cycle index.An analog circuit with five sinusoidal cycles is used as the folding amplifier ( Figure 3) [31. Seven sinusoids uniformly spaced in phase are interpolated between two folding amplifiers with quadrature outputs (I and Q) by a circular interpolation ladder, consisting of resistors whose values are determined by a trigonometric relationship (Figure 4). Differential comparators encode the folded signal by sensing the zero crossings of these sinusoids. Errors in the interpolated voltages induced by V, , modulation of the emitter followers driving the ladder exactly cancel at the zero-crossing comparator. Half cycles added to the extremes of the characteristics sense folding amplifier input overrange.Gray coding of the folded thermometer code emerges naturally by applying the outputs of the interpolation ladder to a collection of "analog inverters" (amp...

Analog-to-digital converter survey and analysis

“…In order to overcome these problems, variations on the flash architecture have been developed which use relatively few comparators yet retain good speed. Examples capable of Gs/s rates are the folded-flash [12]- [14]; and pipelined [15], [16] architectures.…”