2020 IEEE 6th World Forum on Internet of Things (WF-IoT) 2020
DOI: 10.1109/wf-iot48130.2020.9221058
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A 10.5µW programmable SAR ADC Frontend with SC Preamplifier for Low-Power IoT Sensor Nodes

Abstract: Massive deployment of wireless autonomous sensor nodes requires their lifetime extension and cost reduction. The analog frontend (AFE) plays a key role in this context. This paper presents a successive approximation register analog-to-digital converter (SAR ADC) with a switched-capacitor programmable gain switched preamplifier (SC PGSA), as a basic component of an integrated ultra-low power AFE. AFE resolution, sample rate and signal gain are configurable between 6 to 13 bit, 1 to 10 kS/s and -6 to 12 dB, resp… Show more

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Cited by 5 publications
(7 citation statements)
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“…Where the charge injection is defned as the charge that exists between the source and drain terminals when the sample switch is turned of, and the clock feed through is defned as the charge injected due to the overlapping coupling capacitor between the gate and drain terminals. Consequently, it is preferable to implement the sample switch by using CMOS transmission gates [8,64,103] or the bootstrap switch in Figure 4 [2,5,6,11,17,22,24,31,34,45,53,58,63,65 Te variations in conductivity are reduced by utilizing the CMOS transmission gates, but the problem of input dependence still exists. Additionally, a large parasitic capacitor that limits the resolution of SAR appears.…”
Section: Sar Sample and Hold Circuitmentioning
confidence: 99%
See 2 more Smart Citations
“…Where the charge injection is defned as the charge that exists between the source and drain terminals when the sample switch is turned of, and the clock feed through is defned as the charge injected due to the overlapping coupling capacitor between the gate and drain terminals. Consequently, it is preferable to implement the sample switch by using CMOS transmission gates [8,64,103] or the bootstrap switch in Figure 4 [2,5,6,11,17,22,24,31,34,45,53,58,63,65 Te variations in conductivity are reduced by utilizing the CMOS transmission gates, but the problem of input dependence still exists. Additionally, a large parasitic capacitor that limits the resolution of SAR appears.…”
Section: Sar Sample and Hold Circuitmentioning
confidence: 99%
“…Due to their lowest number of transistors, this scheme saves both power and area. Te basic structure of the single-stage dynamic latch comparator [3,4,6,16,63,86,94] is presented in Figure 5. It consists of three sections, including the diferential amplifcation section (M1 and M2), the cross-coupled inverter section (M3:M6), and the reswitched section (S1:S4).…”
Section: Single-stage Dynamic Latchmentioning
confidence: 99%
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“…With the advent of the Internet of Things (IoT), the usage of sensor networks for various applications has seen an explosive growth. As a starting point on the road to autonomous, harvester-powered (zero power) sensor nodes, the integrated ZeSCIP zero power analog frontend (AFE) was designed to readout typical environmental sensors with microwatt power consumption [1]. It aims at the dynamic IoT market, where short market times and low production costs are an important factor.…”
Section: Introductionmentioning
confidence: 99%
“…It aims at the dynamic IoT market, where short market times and low production costs are an important factor. The sensor data, digitized and pre-processed by ZeSCIP, is available for further processing and transmitting by a microcontroller, which was not taken into account in [1]. In this paper, ZeSCIP is brought into a realistic application scenario by attaching it in a test setup to a microntroller and to commercial sensors.…”
Section: Introductionmentioning
confidence: 99%