A 1-V CMOS audio amplifier for low cost hearing aids

Azzolini, C.; Boni, Andrea

doi:10.1109/icecs.2008.4674915

Cited by 7 publications

(6 citation statements)

References 7 publications

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“…amplifier IC for medical hearing aid and for audio application (Azzolini & Boni, 2008) is also presented. The differential difference amplifier-based non-inverting instrumentation amplifier (Ng & Chan, 2005) for biomedical application and an analogue readout front-end for biomedical application (Yazicioglu, Merken, Puers, & Hoof, 2007) using AC-coupled chopped instrumentation amplifier for filtering 1/f noise and rejecting offset have been discussed.…”

Section: Literature Reviewmentioning

confidence: 99%

Design of quadrature amplitude modulation–based DC offset cancellation circuit

Goswami

Joshi

Pal

2015

International Journal of Electronics Letters

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Section: Literature Reviewmentioning

confidence: 99%

Design of quadrature amplitude modulation–based DC offset cancellation circuit

Goswami

Joshi

Pal

2015

International Journal of Electronics Letters

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“…Previous research proves that the sound pressure level (SPL) received by human beings ranges from 60 dB SPL to 100 dB SPL, and the safe sound level is about 80 dB SPL to 90 dB SPL [5][6][7][8][9]. So the gain of AGC in hearing aid SoC must be adjusted in a wide range of about 40 dB.…”

Section: Basis Of Proposed Psjmentioning

confidence: 99%

“…Also, the input PMOS transistors can minimize the equal input noise due to its low flick noise, which means for the same output amplitude level the SNR is improved [6][7][8][9][10]. In the second stage, Class-AB composition optimizes the output quiescent current, while achieving a larger output swing.…”

Section: Vlsi Designmentioning

confidence: 99%

A 69-dB SNR 89-μW AGC for Multifrequency Signal Processing Based on Peak-Statistical Algorithm and Judgment Logic

Dai

Chen

2016

VLSI Design

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A novel peak-statistical algorithm and judgment logic (PSJ) for multifrequency signal application of Autogain Control Loop (AGC) in hearing aid SoC is proposed in this paper. Under a condition of multifrequency signal, it tracks the amplitude change and makes statistical data of them. Finally, the judgment is decided and the circuit gain is controlled precisely. The AGC circuit is implemented with 0.13 μm 1P8M CMOS mixed-signal technology. Meanwhile, the low-power circuit topology and noise-optimizing technique are adopted to improve the signal-to-noise ratio (SNR) of our circuit. Under 1 V voltage supply, the peak SNR achieves 69.2 dB and total harmonic distortion (THD) is 65.3 dB with 89 μW power consumption.

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“…It is noted that DG open-loop and Db are mainly caused by the effect such as the large output swing [10]. Hence, Eqs.…”

Section: Introductionmentioning

confidence: 98%

Dual-mode gain control for a 1 V CMOS hearing aid device with enhanced accuracy and energy-efficiency

Yang

Liu

et al. 2012

Analog Integr Circ Sig Process

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A dual-mode gain control (DMGC) technique is presented for accurate and energy-efficient pre-amplification in the front-end system of a hearing aid chip. Compared with the conventional automatic gain control (AGC) approach, the DMGC approach is characterized by an amplification switching mechanism between the prolinearity discrete gain setting mode and the energy-efficient AGC mode. Thus, the total harmonic distortion (THD) should be significantly improved without incurring any degradation concerning other performances parameters (e.g. gain, noise and power consumption). In order to further enhance the system power efficiency, a self currentadapting (SCA) circuit design technique is proposed. Such SCA circuits are capable of automatically adjusting the bias current in accordance with the sound level. A prototype chip was designed with a 0.13 lm standard CMOS process and tested with 1 V supply voltage. The measurement results show that, for a typical output level of 500 mV p-p , the THD is somewhere below -64 dB, achieving approximately ten times reduction compared to the previously reported works. The power consumption of less than 45 lW has also been obtained. In addition, the typical input referred noise is only 2 lV rms and the maximum gain attainable is up to 39 dB.

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A 1-V CMOS audio amplifier for low cost hearing aids

Cited by 7 publications

References 7 publications

Design of quadrature amplitude modulation–based DC offset cancellation circuit

Design of quadrature amplitude modulation–based DC offset cancellation circuit

A 69-dB SNR 89-μW AGC for Multifrequency Signal Processing Based on Peak-Statistical Algorithm and Judgment Logic

Dual-mode gain control for a 1 V CMOS hearing aid device with enhanced accuracy and energy-efficiency

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