A 1 V 92 dB SNDR 10 kHz Bandwidth Second-Order Asynchronous Delta-Sigma Modulator for Biomedical Signal Processing

Kledrowetz, Vilém; Fujcik, Lukáš; Prokop, Roman; Háze, Jiří

doi:10.3390/s20154137

Cited by 5 publications

(4 citation statements)

References 27 publications

(38 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The proposed modulator is a 2 nd -order CTΣΔM with CIFF architecture that consists of a CT loop filter, single-bit quantizer, and resistive DAC as shown in Figure 11. Fully differential architecture implementation minimizes even-order harmonics and common-mode noise [22]. The circuits implemented with active RC integrators are highly linear, insensitive to parasitics, and simple to design.…”

Section: Second-order Ctσδmmentioning

confidence: 99%

Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal Acquisition

Kavitha

Akhila²,

Kannan

2023

Eng. Technol. Appl. Sci. Res.

View full text Add to dashboard Cite

The recent developments in biosignal acquisition devices for continuous supervision of cardiovascular signs of high-risk patients require a high-precision and low-power Analog Front End (AFE) circuit. The proposed design adopts Continuous-Time (CT) Sigma-Delta Modulator (ΣΔM) architecture to achieve high resolution and SIgnal-to-Noise And Distortion ratio (SINAD) requirements. The proposed modulator is a second-order CT-ΣΔM with Cascade of Integrators Feed-Forward (CIFF) architecture that consists of a CT loop filter, a single-bit quantizer, and a Digital-to-Analog Converter (DAC). The use of single-bit quantization in the design reduces circuit complexity and power consumption. To use the designed ΣΔM for measuring ECG signals, a bandwidth (Bw) of 150 Hz is considered with a sampling frequency (fs) of 153.6kHz to achieve an oversampling ratio of 512. The design is simulated in a standard Cadence Virtuoso EDA tool at 180nm CMOS technology, operating at 1.8V supply voltage at the block level. The simulation results for the designed modulator show that SINAD is 104.5dB, the Effective Number Of Bits (ENOB) is 17.06bits, with power consumption of 24µW, and achieves Schreier’s Figure-Of-Merit (FOM) equal to 172.45dB.

show abstract

Section: Second-order Ctσδmmentioning

confidence: 99%

Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal Acquisition

Kavitha

Akhila²,

Kannan

2023

Eng. Technol. Appl. Sci. Res.

View full text Add to dashboard Cite

show abstract

“…Then, the PGA’s output signal is converted into a digital one for further signal processing. A suitable type of ADC could be an asynchronous delta-sigma modulator presented in [ 2 ] or a continuous delta-sigma modulator [ 20 ]; both have implicit antialiasing filters, low power consumption, or relaxed requirements on analog circuits.…”

Section: The Proposed Structure Of the Analog Front-end (Afe)mentioning

confidence: 99%

“…Filtering is followed by converting an analog signal into a digital signal, which enables further digital signal processing (DSP). The delta-sigma analog-to-digital converter (ADC) is currently one the most popular types of ADC architecture in biomedical signal processing, owing to its power efficiency and high resolution [ 1 , 2 , 3 ]. It is also possible to implement only a delta-sigma modulator on a wearable sensor integrated circuit (IC) when a stream of single bits from the modulator´s output (PDM) is transmitted via wireless communication to a computer [ 4 , 5 ].…”

Section: Introductionmentioning

confidence: 99%

A Fully Differential Analog Front-End for Signal Processing from EMG Sensor in 28 nm FDSOI Technology

Kledrowetz

Prokop

Fujcik

et al. 2023

Sensors

Self Cite

View full text Add to dashboard Cite

This paper presents a novel analog front-end for EMG sensor signal processing powered by 1 V. Such a low supply voltage requires specific design steps enabled using the 28 nm fully depleted silicon on insulator (FDSOI) technology from STMicroelectronics. An active ground circuit is implemented to keep the input common-mode voltage close to the analog ground and to minimize external interference. The amplifier circuit comprises an input instrumentation amplifier (INA) and a programmable-gain amplifier (PGA). Both are implemented in a fully differential topology. The actual performance of the circuit is analyzed using the corner and Monte Carlo analyses that comprise fifth-hundred samples for the global and local process variations. The proposed circuit achieves a high common-mode rejection ratio (CMRR) of 105.5 dB and a high input impedance of 11 GΩ with a chip area of 0.09 mm2.

show abstract

“…e first one is the single-loop and the second is the multiloop. A major drawback of the multiloop architecture is that precise matching of the analog and digital signal processing paths is required to avoid large errors caused by integrator gain coefficient variations [28]. To reduce the noise and nonlinearity of the system, the proposed CDA adopts a secondorder single-feedback loop structure [29,30].…”

Section: Closed-loop Negative Feedbackmentioning

confidence: 99%

High-Fidelity and High-Efficiency Digital Class-D Audio Power Amplifier

Wei

et al. 2021

Journal of Electrical and Computer Engineering

View full text Add to dashboard Cite

This study presents a high-fidelity and high-efficiency digital class-D audio power amplifier (CDA), which consists of digital and analog modules. To realize a compatible digital input, a fully digital audio digital-to-analog converter (DAC) is implemented on MATLAB and Xilinx System Generator, which consists of a 16x interpolation filter, a fourth-order four-bit quantized delta-sigma (ΔΣ) modulator, and a uniform-sampling pulse width modulator. The CDA utilizes the closed-loop negative feedback and loop-filtering technologies to minimize distortion. The audio DAC, which is based on a field-programmable gate array, consumes 0.128 W and uses 7100 LUTs, which achieves 11.2% of the resource utilization rate. The analog module is fabricated in a 0.18 µm BCD technology. The postlayout simulation results show that the CDA delivers an output power of 1 W with 93.3% efficiency to a 4 Ω speaker and achieves 0.0138% of the total harmonic distortion (THD) with a transient noise for a 1 kHz input sinusoidal test tone and 3.6 V supply. The output power reaches up to 2.73 W for 1% THD (with transient noise). The proposed amplifier occupies an active area of 1 mm2.

show abstract

A 1 V 92 dB SNDR 10 kHz Bandwidth Second-Order Asynchronous Delta-Sigma Modulator for Biomedical Signal Processing

Cited by 5 publications

References 27 publications

Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal Acquisition

Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal Acquisition

A Fully Differential Analog Front-End for Signal Processing from EMG Sensor in 28 nm FDSOI Technology

High-Fidelity and High-Efficiency Digital Class-D Audio Power Amplifier

Contact Info

Product

Resources

About