2018 15th IEEE India Council International Conference (INDICON) 2018
DOI: 10.1109/indicon45594.2018.8987113
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A 1-V, 8.6-nA Resistor-less PTAT Current Reference with Startup Circuit

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“…To reduce this delay, a startup arrangement comprising of M 10 , M 11 and C S is added to the circuit. A similar kind of startup circuit is discussed in [12]. In Figure 3, when the circuit is switched on and before it reaches the steady state, initially the gates of M 1,2 and M 3,4 are at zero volt and V DD respectively.…”
Section: Log Domain Filtermentioning
confidence: 99%
“…To reduce this delay, a startup arrangement comprising of M 10 , M 11 and C S is added to the circuit. A similar kind of startup circuit is discussed in [12]. In Figure 3, when the circuit is switched on and before it reaches the steady state, initially the gates of M 1,2 and M 3,4 are at zero volt and V DD respectively.…”
Section: Log Domain Filtermentioning
confidence: 99%