A 1-V–0.6-V 9-b 1.5-MS/s Reference-Free Charge-Sharing SAR ADC for Wireless-Powered Implantable Telemetry

Tsai, Jen-Huan; Wang, Hui-Huan; Chen, Yen–Ju; Wei, Yen-Hsin; Kao, Yo-Hsien; Yen, Yang-Chi; Huang, Po-Chiun; Shen, Meng-Hung; Chen, Hsin

doi:10.1109/tcsii.2014.2345304

Cited by 7 publications

(7 citation statements)

References 9 publications

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“…In the case of CT-IΣ∆ ER , only the 2 nd -order CT IΣ∆ modulator and the on-chip analog buffers were fabricated. As for the 8-bit SAR ADC, an area of 0.3 mm 2 is estimated according to [25], in which a SAR ADC was implemented in the same technology node. A power consumption of 0.85 µW at 8 kS/s is also estimated for the 8-bit SAR ADC according to [25].…”

Section: Resultsmentioning

confidence: 99%

“…The measured performance is summarized in Table II. As the SAR ADC was not implemented onchip, a power consumption of 0.85 at 8 kS/s is estimated for the 8-bit SAR ADC according to [24]. When comparing the measured SNDRs with the post-layout transient noise simulation performance presented in Figure 13, there is around 3.8-dB degradation in all three cases.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…Summary of measured performance. MHz clock frequency (instead of 2.56 MHz) was used because of the limited sampling resolution of the logic analyzer.A 0.85 consumption is estimated for the SAR ADC[24].The area of the 8-bit SAR ADC is estimated as 0.30[24].…”

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confidence: 99%

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A comparative design study of continuous‐time incremental sigma‐delta ADC architectures

Tao

Rusu

2016

Circuit Theory & Apps

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A Comparative Design Study of Continuous-Time Incremental Sigma-Delta ADC Architectures. International journal of circuit theory and applications, : 1-16Access to the published version may require subscription. SUMMARYThis paper presents a comparative design study of continuous-time (CT) incremental sigma-delta (IΣ∆) ADCs, which can expand another dimension of the IΣ∆ ADC world that is dominated by discrete-time implementations. Several CT IΣ∆ ADC architectures are introduced and analyzed aiming to reduce the modulator's sampling frequency and consequently the power dissipation. Based on the analytical results, three CT IΣ∆ ADCs are selected to be examined, implemented, and tested. The three ADC prototypes, fabricated in a standard 0.18 µm CMOS technology, demonstrate competitive figure-of-merits in terms of power efficiency compared to the state-of-the-art counterparts.

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Section: Resultsmentioning

confidence: 99%

Section: Measurement Resultsmentioning

confidence: 99%

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A comparative design study of continuous‐time incremental sigma‐delta ADC architectures

Tao

Rusu

2016

Circuit Theory & Apps

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“…where N OX is the number of oxide layers between the plates of the vertical capacitor. From (7) and (8), the ratio between the occupied chip area of the vertical capacitor and the lateral capacitor is given by…”

Section: F Area Efficiencymentioning

confidence: 99%

Matching Properties of Femtofarad and Sub-Femtofarad MOM Capacitors

Omran

Alahmadi

Salama

2016

IEEE Trans. Circuits Syst. I

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Small metal-oxide-metal (MOM) capacitors are essential to energy-efficient mixed-signal integrated circuit design. However, only few reports discuss their matching properties based on large sets of measured data. In this paper, we report matching properties of femtofarad and sub-femtofarad MOM vertical-field parallel-plate capacitors and lateral-field fringing capacitors. We study the effect of both the finger-length and finger-spacing on the mismatch of lateral-field capacitors. In addition, we compare the matching properties and the area efficiency of vertical-field and lateral-field capacitors. We use direct mismatch measurement technique, and we illustrate its feasibility using experimental measurements and Monte Carlo simulations. The test-chips are fabricated in a 0.18 μm CMOS process. A large number of test structures is characterized (4800 test structures), which improves the statistical reliability of the extracted mismatch information. Despite conventional wisdom, extensive measurements show that vertical-field and lateral-field MOM capacitors have the same matching properties when the actual capacitor area is considered. Measurements show that the mismatch depends on the capacitor area but not on the spacing; thus, for a given mismatch specification, the lateral-field MOM capacitor can have arbitrarily small capacitance by increasing the spacing between the capacitor fingers, at the expense of increased chip area. Index Terms-Analog-to-digital converter (ADC), capacitanceto-digital converter (CDC), capacitive digital-to-analog converter (CapDAC), capacitor mismatch, energy-efficient circuits, metaloxide-metal (MOM) capacitors, mismatch characterization, programmable capacitor array (PCA). I. INTRODUCTION C APACITANCE sets a fundamental limit for the energy consumed in electronic circuitry. The energy required to charge a capacitor (C) to a voltage (V) is given by CV 2 ; thus, the smaller the capacitance the smaller the energy consumed. Energy efficiency of digital circuitry has been steadily Manuscript

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“…Low speed, high-resolution SAR ADCs are reported in the literature for very low bandwidth applications [8,9]. On the contrary, moderate resolution ADCs having a sampling rate up to 1 MS/s are used in system-on-chip (SoC) measurement and wireless sensor networks [10][11][12]. Further the literature survey reveals efforts in the direction to use medium speed ADCs (few hundreds of kS/s) with circuit techniques for reducing power consumption in low bandwidth regime [13][14][15][16][17][18][19][20].…”

Section: Introductionmentioning

confidence: 99%

Reduced switching mode for SAR ADCs: analysis and design of SAR A‐to‐D algorithm with periodic standby mode circuit components

Joshi

Shrimali

Sharma

2020

IET Circuits, Devices & Systems

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This study presents the analysis and design of reduced switching (RSw) activity mode successive approximation register (SAR) analogue-to-digital (A-to-D) algorithm. For given analogue-to-digital converter (ADC) specifications, RSw mode design is based on the observation that the signal variation in two successive samples becomes linear over a certain range of input frequencies. Hence, dispensable switching activity between the two samples can be eliminated by enabling periodic temporal reference to the converter. No prediction or logic circuitry is required to extract information from previous bits. However, there exists a trade-off between the input frequency and the sampling frequency. A design criterion is derived using numerical mathematics to skip evaluation of the optimum number of bits while maintaining the desired signal-to-noise and distortion ratio. The design criterion is validated through behavioural simulations using MATLAB/Simulink ®. Furthermore, a fully differential 10bit, 104 kS/s ADC is designed in a standard 180 nm CMOS technology to demonstrate circuit implementation of the RSw mode. In the RSw mode, power dissipation in the comparator and relevant digital circuitry decreases by 20%. The ADC achieves lowfrequency effective number of bits of 9.7 bits and spurious free dynamic range of 68.3 dB. With 1.8 V supply voltage, average power dissipation in the core ADC is 2.54 μW; resulting in figure-of-merit of 29.3 fJ/conv-step.

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A 1-V–0.6-V 9-b 1.5-MS/s Reference-Free Charge-Sharing SAR ADC for Wireless-Powered Implantable Telemetry

Cited by 7 publications

References 9 publications

A comparative design study of continuous‐time incremental sigma‐delta ADC architectures

A comparative design study of continuous‐time incremental sigma‐delta ADC architectures

Matching Properties of Femtofarad and Sub-Femtofarad MOM Capacitors

Reduced switching mode for SAR ADCs: analysis and design of SAR A‐to‐D algorithm with periodic standby mode circuit components

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