A 1.8e $^{-}_{\mathrm {rms}} $ Temporal Noise Over 110-dB-Dynamic Range 3.4 $\mu \text{m}$ Pixel Pitch Global-Shutter CMOS Image Sensor With Dual-Gain Amplifiers SS-ADC, Light Guide Structure, and Multiple-Accumulation Shutter

Kobayashi, Masahiro; Onuki, Yusuke; Kawabata, Kazunari; Sekine, Hiroshi; Tsuboi, Takayuki; Matsukawa, Takashi; Akiyama, T.; Matsuno, Yasushi; Takahashi, Hidekazu; Koizumi, Toru; Sakurai, Katsuhito; Yuzurihara, Hiroshi; Inoue, Shunsuke; Ichikawa, Takeshi

doi:10.1109/jssc.2017.2737143

Cited by 24 publications

(20 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Even with the 100 dB difference in the illumination levels, all the color objects are clearly captured without saturation. A. Tournier et.al [3] T. Yokoyama et.al [5] M. Kobayashi et.al [6] L. Stark et.al [9] T. Kondo et.al [8] I. Takayanagi et.al [13,14] Process…”

Section: Fabrication and Characterization Resultsmentioning

confidence: 99%

“…Due to this structure, in the GS pixel, an additional in-pixel analog memory is needed to store the signal until it is read out from the pixel array. Generally, there are two approaches for the in-pixel analog memory; one is to store the signal charge before the charge-to-voltage conversion takes place, which is referred to as the charge domain GS pixel [1][2][3][4][5][6], and the other is to is to store a voltage signal after the charge is converted to a voltage, which is referred to as the voltage domain GS pixel [7][8][9]. These two approaches can be realized by both the front-side-illuminated (FSI) devices and the back-side-illuminated (BSI) devices.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Stacked Back Side-Illuminated Voltage Domain Global Shutter CMOS Image Sensor with a 4.0 μm Multiple Gain Readout Pixel

Miyauchi¹,

Mori²,

Otaka³

et al. 2020

Sensors

View full text Add to dashboard Cite

A backside-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor with 4.0 μm voltage domain global shutter (GS) pixels has been fabricated in a 45 nm/65 nm stacked CMOS process as a proof-of-concept vehicle. The pixel components for the photon-to-voltage conversion are formed on the top substrate (the first layer). Each voltage signal from the first layer pixel is stored in the sample-and-hold capacitors on the bottom substrate (the second layer) via micro-bump interconnection to achieve a voltage domain GS function. The two sets of voltage domain storage capacitor per pixel enable a multiple gain readout to realize single exposure high dynamic range (SEHDR) in the GS operation. As a result, an 80dB SEHDR GS operation without rolling shutter distortions and motion artifacts has been achieved. Additionally, less than −140dB parasitic light sensitivity, small noise floor, high sensitivity and good angular response have been achieved.

show abstract

Section: Fabrication and Characterization Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Stacked Back Side-Illuminated Voltage Domain Global Shutter CMOS Image Sensor with a 4.0 μm Multiple Gain Readout Pixel

Miyauchi¹,

Mori²,

Otaka³

et al. 2020

Sensors

View full text Add to dashboard Cite

show abstract

“…Within a certain conversion time, the required counting clock frequency is reduced which will reduce the power consumption. Based on the above analysis, multiple-ramp [12], nonlinear-slope [9,13,14], and gain-adaptive [7,15,16] techniques have been proposed to realize high A/D resolution in a short conversion time, which is shown in Figure 4. The multiple-ramp signal path occupies more area and the calibration of offset errors among different ramps is difficult.…”

Section: Concept Of Gain-adaptive Ss-adcmentioning

confidence: 99%

“…Thousands of SS-ADCs work simultaneously and the counting clock usually goes up to several GHz, which makes the power consumption quite high. In high resolution CISs, the power consumption of the SS-ADCs, which is over 40% of that of the entire CIS [7], has become a major problem. The trade-off between power consumption and conversion time has become a big challenge in the design of SS-ADC.…”

Section: Introductionmentioning

confidence: 99%

A Low-Power Column-Parallel Gain-Adaptive Single-Slope ADC for CMOS Image Sensors

Wei

Sun

et al. 2020

Electronics

View full text Add to dashboard Cite

A low-power column-parallel gain-adaptive single-slope analog-to-digital converter (ADC) for CMOS image sensors is proposed. The gain-adaptive function is realized with the proposed switched-capacitor based gain control structure in which only minor changes from the traditional single-slope ADC are required. A switched-capacitor controlled dynamic bias comparator and a flip-reduced up/down double-data-rate (DDR) counter are proposed to reduce the power consumption of the column circuits. A 12-bit current steering digital-to-analog converter (DAC) with a two-dimensional gradient error tolerant switching scheme is adopted in the ramp generator to improve the linearity of the ADC. The proposed techniques were experimentally verified in a prototype chip fabricated in the TSMC 180 nm CMOS process. A single-column ADC consumes a total power of 63.2 μ W and occupies an area of 4.48 μ m × 310 μ m. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) of the ADC are −0.43/+0.46 least significant bit (LSB) and −0.84/+1.95 LSB. A 13-bit linear output is acquired in nonlinearity within 0.08% of the full scale after calibration.

show abstract

“…Wide dynamic range CMOS image sensor, also considered very important parameter in determining the sensor performance. Wide dynamic range increases the sensor's ability to capture the details of the image under low and high light conditions [3].…”

Section: Introductionmentioning

confidence: 99%

Design and Simulation of 140 dB Dynamic Range and 20 uVrms Readout Noise CMOS Image Sensor

Makkey

2021

Menoufia Journal of Electronic Engineering Research

View full text Add to dashboard Cite

This paper provides the design, simulation and implementation of a very wide dynamic range and a low readout noise CMOS image sensor (CIS) with high sensitivity by using a diode connected transistors in parallel with floating diffusion node and sensor output. The sensor is simulated, designed and implemented in a 130 nm CMOS technology using cadence tool. The area of the proposed pixel reaches to 3 um x 3 um and consists of seven NMOS transistors and one capacitor. The readout circuit has the following parameters as very low output noise of 20 uVrms with a 5 MHz bandwidth for pixel circuitry. Power dissipation of 10 uW was achieved at an operation voltage of 1.6 V for pixel circuitry. The proposed sensor has good features of low noise and a 140 dB wide dynamic range due to the diode connected transistor configuration that has been used. This paper provides the effect of adding a diode connected transistors M7 and M8 on an increasing dynamic range of CMOS image sensor to 140 dB and reducing its readout noise to 20 uVrms. Also, this paper provides a mathematical simulation of noise model of CIS using Matlab and cadence.

show abstract

A 1.8e $^{-}_{\mathrm {rms}} $ Temporal Noise Over 110-dB-Dynamic Range 3.4 $\mu \text{m}$ Pixel Pitch Global-Shutter CMOS Image Sensor With Dual-Gain Amplifiers SS-ADC, Light Guide Structure, and Multiple-Accumulation Shutter

Cited by 24 publications

References 2 publications

A Stacked Back Side-Illuminated Voltage Domain Global Shutter CMOS Image Sensor with a 4.0 μm Multiple Gain Readout Pixel

A Stacked Back Side-Illuminated Voltage Domain Global Shutter CMOS Image Sensor with a 4.0 μm Multiple Gain Readout Pixel

A Low-Power Column-Parallel Gain-Adaptive Single-Slope ADC for CMOS Image Sensors

Design and Simulation of 140 dB Dynamic Range and 20 uVrms Readout Noise CMOS Image Sensor

Contact Info

Product

Resources

About