A 1.85GHz CMOS power amplifier with zero-voltage-switching contour-based outphasing control to improve back-off efficiency

Shim, Sunbo; Pamarti, Sudhakar

doi:10.1109/mwsym.2015.7166962

Cited by 4 publications

(6 citation statements)

References 6 publications

(8 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, the presented model can also be applied to any other implementations of OEPAs e.g. to OEPAs with a so-called parallel class-E design [14].…”

Section: Vin Max(vin)mentioning

confidence: 99%

A +20 dBm Highly Efficient Linear Outphasing Class-E PA Without AM/AM and AM/PM Characterization Requirements

Ghahremani

Annema

Nauta

2019

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

Outphasing Class-E Power Amplifiers (OEPAs) using isolating power combiners and an inverse cosine signal component separator are inherently linear but suffer from low efficiency at power back-off. For high efficiency both at maximum output power and at power back-off, non-isolating power combiners are required. In this work the linearity of OEPAs using nonisolating power combiners is studied theoretically and validated by measurement of a 1.8GHz 20dBm OEPA implemented in a standard 65nm CMOS technology using an off-chip transmissionline based combiner. The developed theoretical model for the linearity is then employed to define digital pre-distortion (DPD) parameters for the implemented OEPA. Using this theory-based DPD and without any AM/AM and AM/PM characterizations,-31dB RMS EVM level and below-30dB ACLR were measured for a 13.1dBm 6.25MHz 30Mbit/s 7dB PAPR 64QAM signal with 41.8% drain efficiency and 33.6% power added efficiency.

show abstract

“…However, the presented model can also be applied to any other implementations of OEPAs e.g. to OEPAs with a so-called parallel class-E design [14].…”

Section: Vin Max(vin)mentioning

confidence: 99%

A +20 dBm Highly Efficient Linear Outphasing Class-E PA Without AM/AM and AM/PM Characterization Requirements

Ghahremani

Annema

Nauta

2019

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

show abstract

“…The performance of power amplifiers (PAs), which are representative wasteful blocks in the system, is dramatically decreased as the PAPR increases. This is because the PA needs to be operated at a backed‐off peak linear output power to prevent distortion in the modulated signal; therefore, the PA has low output power and efficiency . Unfortunately, the problem becomes more severe in CMOS process, which has a low break down voltage of the transistor and lossy silicon substrate .…”

Section: Introductionmentioning

confidence: 99%

A study comparing current and voltage combining techniques for CMOS power amplifiers for WLAN applications

Park

Lee

Park

2019

Micro & Optical Tech Letters

View full text Add to dashboard Cite

This article presents CMOS power amplifiers for WLAN applications. These power amplifiers use current and voltage combining techniques for simultaneous improvement of the output power and efficiency, respectively, and are analyzed to determine which technique is more suitable for WLAN applications. The power amplifiers are fabricated with a 180 nm CMOS process. Their performance is verified using an 802.11 g modulated signal with 64 QAM, 20 MHz of bandwidth, and 54‐Mbps at 2.7 GHz. The measurements of the current and voltage combining power amplifiers show about 21.9 and 21.8 dBm of average output power, respectively, at −25 dB error vector magnitude (EVM), and about 20.2 and 18 dBm of average output power, respectively, at −30 dB EVM for a commercial specification. In addition, the current combining PA is operated in a multi‐mode manner, which saves the power stage current about 225 mA of the power stage current at low power mode. No pre‐distortion technique is required and all components are integrated on the chip.

show abstract

“…In [10], variable duty cycle combined with variable drain capacitance and with a tunable load network were used to maintain ZVS and ZSS conditions in power back-off up to (ideally) 9dB back-off. The CMOS implementation of the technique, presented in [10], was employed in [11] at 1.85GHz. For higher than (ideally) 9dB back-off levels, the outphasing technique employed in [10], [11] resulted in a reduction of the efficiency due to non-zero switching losses (non-ZVS condition).…”

Section: Introductionmentioning

confidence: 99%

“…The CMOS implementation of the technique, presented in [10], was employed in [11] at 1.85GHz. For higher than (ideally) 9dB back-off levels, the outphasing technique employed in [10], [11] resulted in a reduction of the efficiency due to non-zero switching losses (non-ZVS condition). Due to practical limitations on the minimum feasible duty cycle at high frequencies in [11], the ZVS and ZSS conditions were satisfied for 6dB of back-off range which yielding lower than 10% Power Added Efficiency (PAE) at 10dB back-off.…”

Section: Introductionmentioning

confidence: 99%

“…Moreover, it was shown that this technique also improves the OPDR and reduces switch voltage stress at back-off. In contrast to [10], [11], in [7] we used a load-insensitive design which ideally yields 100% efficiency at (almost) 0dB and 10dB back-off levels and more than 95% efficiency between 0dB and 12dB back-off levels. Moreover, theoretically this yields an infinite OPDR without requiring to tune any parameter.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Outphasing Class-E Power Amplifiers: From Theory to Back-Off Efficiency Improvement

Ghahremani

Annema

Nauta

2018

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

Abstract-This paper presents an analysis of outphasing class-E Power Amplifiers (OEPAs), using load-pull analyses of single class-E PAs. This analysis is subsequently used to rotate and shift power contours and rotate the efficiency contours to improve the efficiency of OEPAs at deep power back-off, to improve the Output Power Dynamic Range (OPDR) and to reduce switch voltage stress. To validate the theory a 65nm CMOS prototype, using a pcb transmission-line based power combiner was implemented. The OEPA provides +20.1dBm output power from VDD=1.25V at 1.8GHz with more than 65% Drain Efficiency (DE) and 60% Power Added Efficiency (PAE). The presented technique enables more than 49dB OPDR and 37% DE and 22% PAE at 12dB back-off with reduced switch voltage stress.

show abstract

A 1.85GHz CMOS power amplifier with zero-voltage-switching contour-based outphasing control to improve back-off efficiency

Cited by 4 publications

References 6 publications

A +20 dBm Highly Efficient Linear Outphasing Class-E PA Without AM/AM and AM/PM Characterization Requirements

A +20 dBm Highly Efficient Linear Outphasing Class-E PA Without AM/AM and AM/PM Characterization Requirements

A study comparing current and voltage combining techniques for CMOS power amplifiers for WLAN applications

Outphasing Class-E Power Amplifiers: From Theory to Back-Off Efficiency Improvement

Contact Info

Product

Resources

About