A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM

Nambu, H.; Kanetani, K.; Yamasaki, K.; Higeta, K.; Usami, M.; Fujimura, Y.; Ando, Keiichi; Kusunoki, T.; Yamaguchi, K.; Homma, N.

doi:10.1109/4.726553

Cited by 44 publications

(6 citation statements)

References 32 publications

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“…The main improvements of our tool compared to CACTI/eCACTI are the following: * More optimal decode topologies [1] and circuits [16] DIN CLK same wire characteristics for all interconnects, as is being done by CACTI and eCACTI), and accurate analytical modeling of these structures. In addition, a realistic BEOL-stack3 was used for each technology node.…”

Section: Experimental Methodologymentioning

confidence: 99%

Energy/Power Breakdown of Pipelined Nanometer Caches (90nm/65nm/45nm/32nm)

Rodríguez¹,

Jacob²

2006

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design

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As transistors continue to scale down into the nanometer regime, device leakage currents are becoming the dominant cause of power dissipation in nanometer caches, making it essential to model these leakage effects properly. Moreover, typical microprocessor caches are pipelined to keep up with the speed of the processor, and the effects ofpipelining overhead need to be properly accounted for.In this paper, we present a detailed study of pipelined nanometer caches with detailed energy/power dissipation breakdowns showing where and how the power is dissipated within a nanometer cache. We explore a three-dimensional pipelined cache design space that includes cache size (16kB to 512kB), cache associativity (directmapped to 16-way) and process technology (9Onm, 65nrn, 45nm and 32nm).Among our findings, we show that cache bitline leakage is increasingly becoming the dominant cause of power dissipation in nanometer technology nodes. We show that subthreshold leakage is the main cause of static power dissipation, and that gate leakage is, surprisingly, not a significant contributor to total cache power, even for 32nm caches. We also show that accounting for cache pipelining overhead is necessary, as power dissipated by the pipeline elements is a significant part ofcache power.

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Section: Experimental Methodologymentioning

confidence: 99%

Energy/Power Breakdown of Pipelined Nanometer Caches (90nm/65nm/45nm/32nm)

Rodríguez¹,

Jacob²

2006

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design

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“…Fig. 11 shows a typical structure of row decoder in the synchronous SRAM with clock Φ to separate the pre-charge (Φ = 0) and evaluation phase (Φ = 1) [23]. When Φ = 0, the output of WL is low to make the access transistors in the off state.…”

Section: Appendix a Influence Of Voltage Reduction On Peripheral Cirmentioning

confidence: 99%

Resp

Zheng

Hashemian

Bhunia

2013

Proceedings of the 50th Annual Design Automation Conference

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Physical Unclonable Functions (PUFs) have emerged as an attractive primitive to address diverse hardware security issues in Integrated Circuits (ICs). A majority of existing PUFs rely on a dedicated circuit structure for generating chip-specific signatures, which often imposes concerns due to area/power overhead and extra design efforts. Furthermore, existing PUF-based signature generation cannot be employed to authenticate chips already in the market. In this paper, we propose RESP, a novel PUF structure realized in embedded SRAM array, a prevalent component in processors and system-on-chips (SOCs), with virtually no design modification. RESP leverages on voltage-depend memory access failures (during write) to produce large volume of high-quality challenge-response pairs. Since many modern ICs integrate SRAM array of varying size with isolated power grid, RESP can be easily retrofitted into these chips. Circuit-level simulation of 1000 chips using realistic process variation model shows high uniqueness of 49.2% average inter-die Hamming distance and good reproducibility of 2.88% intra-die Hamming distance under temperature < 85 • C. The device aging effect, e.g. bias temperature instability (BTI), results in only 4.95% estimated unstable bits for ten-year usage.

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“…To guarantee functionality, the delay chain has to be designed for worst case conditions, which means that the clock circuit must be padded in the nominal case, degrading performance. Replica-based delay elements, by virtue of their good tracking, offer the possibility of designing SRAM's with tight specifications across all process corners [22]. Two ways of creating and using these replica structures are explained in the following sections.…”

Section: Clock Matchingmentioning

confidence: 99%

A replica technique for wordline and sense control in low-power SRAM's

Amrutur¹,

Horowitz²

1998

IEEE J. Solid-State Circuits

166

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With the migration toward low supply voltages in low-power SRAM designs, threshold and supply voltage fluctuations will begin to have larger impacts on the speed and power specifications of SRAM's. We present techniques based on replica circuits which minimize the effect of operating conditions' variability on the speed and power. Replica memory cells and bitlines are used to create a reference signal whose delay tracks that of the bitlines. This signal is used to generate the sense clock with minimal slack time and control wordline pulsewidths to limit bitline swings. We implemented the circuits for two variants of the technique, one using bitline capacitance ratioing in a 1.2-m 8-kbyte SRAM, and the other using cell current ratioing in a 0.35m 2-kbyte SRAM. Both the RAM's were measured to operate over a wide range of supply voltages, with the latter dissipating 3.6 mW at 150 MHz at 1 V and 5.2 W at 980 kHz at 0.4 V.

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A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM

Cited by 44 publications

References 32 publications

Energy/Power Breakdown of Pipelined Nanometer Caches (90nm/65nm/45nm/32nm)

Energy/Power Breakdown of Pipelined Nanometer Caches (90nm/65nm/45nm/32nm)

Resp

A replica technique for wordline and sense control in low-power SRAM's

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