A 1.8-GHz instruction window buffer for an out-of-order microprocessor core

Leenstra, J.; Pille, J.; Müller, A.; Sauer, Wolfram; Sautter, R.; Wendel, D.

doi:10.1109/4.962282

Cited by 10 publications

(8 citation statements)

References 12 publications

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“…The heterogeneous array of small processing units is connected by a network for operand and instruction communication. In contrast to classic centralized schedulers [53], forwarding of result tags is replaced with dedicated operand transport instructions. Each FU forms a separate cluster with a private register file.…”

Section: Extending Tomasulo_s Scheme For Clustered Smt Architectures mentioning

confidence: 99%

A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance

Berekovic

Niggemeier

2007

J Sign Process Syst Sign Image

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A scalable, distributed, processor architecture is presented that emphasizes on high performance computing for digital signal processing applications by combining high frequency design techniques with a very high degree of parallel processing on a chip. The architecture is based on a superscalar processor model with a modified Tomasulo scheme that was extended to eliminate all central control structures for the data flow and to support simultaneous instruction issue from multiple independent threads [simultaneously multi-threaded (SMT)]. Consequent application of fine clustering reduces the cycle-time for wire-sensitive building blocks of the processor like the register file and the scheduling window and leads to a distributed architecture model, where independent thread processing units, arithmetic logic units, registers files and memories are distributed across the chip and communicate with each other by special network. A special communication protocol replaces broadcasting and associative compare of destination tags in a centralised instruction scheduler with explicit operand transfer instructions, thus decentralizing the control of the data flow to the greatest extent. As a result, the processor cycle time does neither depend on the issue bandwidth of a single thread nor on the execution bandwidth of the SMT processor. This makes the performance of the architecture scalable with both the number of function and the number of thread units without having any impact on the processors cycle-time. Performance and scalability of the proposed microarchitecture is demonstrated with critical signal processing kernels from the MPEG-4 video coding standard on a cycle-true simulator.

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Section: Extending Tomasulo_s Scheme For Clustered Smt Architectures mentioning

confidence: 99%

A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance

Berekovic

Niggemeier

2007

J Sign Process Syst Sign Image

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“…Although there has been some research efforts to remove the CAM logic with different schemes like using a FIFO queue implementation [7] or dependence matrices [24], contemporary processors still use a CAM based design to avoid any performance degradation [20] [25].…”

Section: Introductionmentioning

confidence: 99%

Tag simplification: Achieving power efficiency through reducing the complexity of the wakeup logic

Aykenar

Ozgur

Bayraktar

et al. 2011

2011 International Conference on Energy Aware Computing

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Contemporary microprocessor cores employ out-of-order execution in order to boost performance. One of the artifacts of the out-of-order execution is the Content Addressable Memory (CAM) cells that allow comparison of the incoming data with the stored value. Many components use these cells inside the processor such as the Issue Queue (IQ), which holds the instructions until their source operands are ready. These processor components receive lookup data each cycle and dissipate significant energy for the comparison operation.In this paper we propose a methodology to remove the capacitive load from the lookup buses and reduce the complexity of the comparison circuitry inside the CAM logic. For demonstration purposes we show the design of a new implementation of the IQ that allows the designers to transfer the complexity to the frontend stages of the processor. Our design reduces the dynamic energy dissipation of the CAM array inside the issue queue 15% with virtually no impact on performance.

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“…Microarchitectural techniques for instruction-level parallelism can be used to achieve increased concurrency in instruction processing [1][2][3]. Out-of-order execution and speculative execution are two powerful techniques that are exploited in modern high-performance processors to increase the amount of concurrency [4][5][6][7]. If the operand data is ready and the required execution resources are free, more concurrency in the pipeline and more performance can be achieved by allowing instructions to be executed out of order.…”

Section: Introductionmentioning

confidence: 99%

Organization and implementation of the register-renaming mapper for out-of-order IBM POWER4 processors

Buti¹,

McDonald

Khwaja³

et al. 2005

IBM J. Res. & Dev.

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We present a new nonconventional approach for designing and organizing register rename mappers that can be applied in modern out-of-order processor chips. A content-addressable memory (CAM) configuration optimal for such a register mapper application was developed. The structure of the CAM and search engine, described in this paper, facilitates the implementation of the register mapper as a group of custom arrays. Each array is dedicated to executing a specific function. Among the functions we implemented are allocation of registers, maintaining the register map and status, source lookup, saving a shadow copy of the register map, and freeing up of registers. We made a novel implementation of the register mapper to provide rename resources for the IBM POWER4e chip, which provides the processing power for the IBM eServere p690. Such register renaming allows for a high level of concurrency in the pipeline and contributes to superior machine performance.

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A 1.8-GHz instruction window buffer for an out-of-order microprocessor core

Cited by 10 publications

References 12 publications

A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance

A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance

Tag simplification: Achieving power efficiency through reducing the complexity of the wakeup logic

Organization and implementation of the register-renaming mapper for out-of-order IBM POWER4 processors

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