2015 IEEE Asian Solid-State Circuits Conference (A-Sscc) 2015
DOI: 10.1109/asscc.2015.7387434
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A 1.74mW/GHz 0.11–2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers

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Cited by 3 publications
(2 citation statements)
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“…With increasing operating frequency, the duty cycle distortion, the reference clock jitter, and the pin-topin delay mismatch adversely affect the valid sampling window. A delay-locked loop (DLL) is often used to achieve a high-quality phase shift or phase alignment for the sampling clock [1][2][3][4][5][6][7][8][9][10][11][12][13][14]. In practice, the routing difference and the different path characteristics of the parallel pins cause considerable pin-to-pin delay mismatch [7].…”
Section: Introductionmentioning
confidence: 99%
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“…With increasing operating frequency, the duty cycle distortion, the reference clock jitter, and the pin-topin delay mismatch adversely affect the valid sampling window. A delay-locked loop (DLL) is often used to achieve a high-quality phase shift or phase alignment for the sampling clock [1][2][3][4][5][6][7][8][9][10][11][12][13][14]. In practice, the routing difference and the different path characteristics of the parallel pins cause considerable pin-to-pin delay mismatch [7].…”
Section: Introductionmentioning
confidence: 99%
“…However, achieving high-frequency operation is difficult because of the requirement for frequency multiplication. In addition, conventional DLLs [2][3][4]6,8,[10][11][12][13][14] only consider the design of the 90 • phase shifter; per-pin deskew is not supported in these DLLs.…”
Section: Introductionmentioning
confidence: 99%