A 1.544 Mb/s CMOS Line Driver for 22.8 Ohm Load

The domain of low-power circuits is expanding to nonportable applications such as telephone central office equipment to satisfy growing needs for higher integration.This paper focuses on the low-power techniques used to design the cloclddata recovery, jitter filter, and the highcurrent line driver circuits in the Quad DS W E P T Line Interface shown in Figure 1. Digital techniques are preferred for clock/data recovery and jitter filtering, over analog approaches because of advantages such as no frequency trimming, instantaneous start-up, false-lock immunity and glitch rejection [l]. Also, their jitter properties are immune to process, temperature and power supply variations. However, to minimize the implicit quantization error, a high frequency clock is required which entails high power dissipation. We have achieved a performance level which with conventional techniques would have required the clock rate to be twice as high as used here. As regards the line driver, the most challenging part is to produce 3V pulses, requiring a peak load current of about 90 mA, roughly twice that needed in a 5V environment. Brief descriptions of these circuits follow. ClocMData RecoveryConceptually (Fig. 2), the sliced data is sampled with a 16x clock (XCLK), validated as positive / negative pulse or no pulse, the timing reference is extracted and the recovered clock (COUT) and data (PDATA, NDATA) are output. The data pulse can occur anywhere in a pulse period and with varying widths due to inter-symbol interference, crosstalk, etc. The clock recovery technique attempts to always center the data pulse-end in its period. A first counter maintains the receiver timing reference by tracking the ideal pulse boundaries. A second counter monitors the pulse width so as to validate it when a preset pulse-width threshold is reached, When a valid pulse is detected, its sign, value and timing are transferred to the output circuit which provides storage and time-out functions for the recovered clock and data. The ideal generated jitter in this case is 0.0625 UI. One can increase the XCLK frequency to meet the DS 1 generated jitter specification of <0.04 U1 (pk-pk). But, this will result in increased power and logic complexity. Therefore, we have used the 16x XCLK and a Data Edge Proximity Detector (Fig. 2), to reduce power and halve the generated jitter. This approach effectively doubles the XCLK frequency with a modest increase in power and logic. The proximity detector samples the data pulse on both edges of XCLK to decide the Jitter filtering refers to the attenuation of phase deviations that occur in the timing signals due to impairments such as crosstalk and intersymbol interference. This is accomplished using a new digital oscillator with reduced quantization and power. Previous digital controlled oscillators, DCOs either add or delete a pulse from the output stream, resulting in an instantaneous phase adjustment equal to an XCLK period. The nominal output is at half the XCLK frequency. The new Edge Suppressing DCO (ES-DCO) utilizes both...

show abstract

“…Previous reports describe fully differential linear drivers and/or complex bias current adjustment schemes [2].…”

Section: Clocmdata Recoverymentioning

confidence: 99%