A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS

An all-digital semi-blind clock and data recovery system

“…The integer portion of the phase is estimated via counters similar to the TDC in [10,11]. The fraction portion is estimated with a different technique similar to [12]. The reference clock is used to sample the multiple phases of the DCO, and detects its transition relative to these phases as shown in Fig.…”

“…JTr is approximated in Eq. (12). The residual input jitter at the OSCDR interface (Jos) in defined in Eq.…”

A novel clock generation algorithm for system-on-chip based on least common multiple

“…The power dissipation of a PLL can be described as sum of a base component -due to frequency independent components, and frequency dependent component -the VCO [22,23]. To prove that the algorithm offers a low power solution, we have considered the recent All Digital PLL (ADPLL) proposed by Lee et al [24].…”

Semidigital PLL Design for Low-Cost Low-Power Clock Generation

“…While integrating a loop filter has been a challenging task in the conventional PLL design, removing the analog loop filter is considered an alternative solution in the recent PLL works [1][2][3][4][5][6][7][8][9][10][11][12][13]. However, the all-digital PLL (ADPLL) requires a high-resolution complex time-to-digital converter (TDC) which requires advanced CMOS technology.…”