A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels

Khairi, Ahmad; Krupnik, Yoel; Laufer, Amir; Segal, Yoav; Cusmai, Marco; Levin, Itamar; Gordon, Ari; Sabag, Yaniv; Rahinski, Vitali; Lotan, Idan; Ori, Gadi; Familia, Noam; Litski, Stas; Grafi, Tali Warshavsky; Virobnik, Udi; Lazar, Dror; Horwitz, Yeshayahu; Balankutty, Ajay; Kiran, Shiva; Palermo, Samuel; Li, Peng Mike; O'Mahony, Frank; Cohen, Ariel

doi:10.1109/jssc.2022.3211475

Cited by 10 publications

(4 citation statements)

References 13 publications

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“…One of our future tasks is to correlate the estimated BER from the simulation with a more advanced FEC [32] like the turbo product code, staircase code, or a low-density parity checking (LDPC) code to further improve the current work for some applications with low latency requirements, e.g., autonomous driving, trading, and AI Chiplet [33]. Additionally, the impact of impairments from other sources, e.g., the quantization noise of the analog-to-digital converter (ADC) [34], on SerDes link with DFE error propagation, needs to be studied in more depth.…”

Section: Discussionmentioning

confidence: 99%

41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology

Zhan,

Li,

Zou

et al. 2023

Electronics

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A high-speed, high-depth pre-interleaver in the proposed symbol pre-interleaving Bit MUX (PBM) was implemented to mitigate decision feedback equalizer (DFE) error propagation in a 400 G Ethernet Serializer–Deserializer (SerDes) interface. Based on the SerDes interface link architecture with 5-tap DFE, the performance of the PBM under DFE error propagation was simulated theoretically, which could obtain an interleaving gain of 0.35 dB. In the pre-interleaver, in order to significantly increase the transmission rate while keeping the larger interleaving depth, characteristic polynomial parallelization with the logic expansion method and register-based memory with interleaving technology were adopted. Finally, the pre-interleaver was fabricated with 65 nm CMOS technology, with a total area of 0.615 mm2, including the I/O pad. The measurement results show that the horizontal opening degree of the output signal can reach 0.925 UI at the data rate of 41.6 Gb/s. The total power consumption is 38.52 mW at the supply voltage of 1.2 V and frequency of 1.3 GHz.

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Section: Discussionmentioning

confidence: 99%

41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology

Zhan,

Li,

Zou

et al. 2023

Electronics

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“…13 is used to ascertain which of its resistances undergo conductivity modulation. R C,N and R C,P lie along the main current path, where there are excess minority carriers; both of those resistances are conductivity modulated, as indicated in (24). R B,N is in parallel with the base-emitter junction of the n-p-n, whereas R B,P is in series with the base-emitter junction of the p-n-p. As a result, in [63], it was argued that only R B,P , (28), undergoes conductivity modulation; forward recovery in R B,P is evident in an n-well triggered SCR's turnon transient.…”

Section: B Silicon-controlled Rectifier (Scr)mentioning

confidence: 99%

“…The most advanced wireline transceivers in development operate at data rates in the range of 112-224 Gb/s, corresponding to Nyquist frequencies in the range of 28-56 GHz [21], [22], [23], [24]. The total capacitance at the IO pin, contributed by the bondpad, ESD protection devices, and input or output transistors, is invariably too large to meet return loss specifications, necessitating the use of bandwidth extension circuits, such as T-coils, and placing tight limits on the allowable ESD capacitance.…”

mentioning

confidence: 99%

Compact Models for Simulation of On-Chip ESD Protection Networks

Rosenbaum,

Huang,

Drallmeier

et al. 2024

IEEE Trans. Electron Devices

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Technology scaling and increased data rates make it near impossible to achieve historic levels of electrostatic discharge (ESD) robustness. This heightens the need for pre-Si verification that a design's ESD level is above a critical value, below which the yield loss and the number of field returns are expected to be high. Transient simulation plays a role in ESD design verification and requires the availability of accurate compact models of the various semiconductor devices, which lie along the discharge path. The compact models included in a foundry process design kit (PDK) are not accurate at ESD current levels. This article describes compact models that have been developed in the ESD device research community. It reviews the measurements used to characterize ESD protection devices and acquire data for model parameter extraction. It is concluded that obtaining accurate measurement data is challenging and this impedes the widescale adoption of ESD compact models.

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“…Due to increasing data bandwidth demand, the PAM4 signaling has been used instead of the NRZ signaling for relaxing the impact of the insertion loss (IL) because required Nyquist frequency of the PAM4 signaling is half compared with that of the NRZ signaling at the same data bandwidth. Furthermore, ADC-based receivers (RXs) [1]- [11] have been adopted instead of analog-based RXs [12]- [15] to handle high-speed multi-level signaling beyond 50 Gb/s in relatively long-distance channels such as middle reach (MR) and long reach (LR), which enables utilizing digital equalization using a DSP after an ADC. Typical ADC-based RXs use baud-rate clock and data recovery (CDR) such as Mueller-Müller (MM) CDR [16], which does not need edge data.…”

Section: Introductionmentioning

confidence: 99%

A Mueller-Müller CDR with False-Lock-Aware Locking Scheme for a 56-Gb/s ADC-Based PAM4 Transceiver

TACHIBANA,

CU NGO,

URAKAWA

et al. 2024

IEICE Trans. Fundamentals

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Although baud-rate clock and data recovery (CDR) such as Mueller-Müller (MM) CDR is adopted to ADC-based receivers (RXs), it suffers from false-lock points when the RXs handle PAM4 data pattern because of the absence of edge data. In this paper, a false-lock-aware locking scheme is proposed to address this issue. After the false-lock-aware locking scheme, a clock phase is adjusted to achieve maximum eye height by using a post-1-tap parameter for an FFE in the CDR loop. The proposed techniques are implemented in a 56-Gb/s PAM4 transceiver. A PLL uses an area-efficient "glasses-shaped" inductor. The RX comprises an AFE, a 28-GS/s 7-bit time-interleaved SAR ADC, and a DSP with a 31-tap FFE and a 1-tap DFE. A TX is based on a 7-bit DAC with a 4-tap FFE. The transceiver is fabricated in 16-nm CMOS FinFET technology, and achieves a BER of less than 1e-7 with a 30-dB loss channel. The measurement results show that the MM CDR escapes from false-lock points, and converges to near the optimum point for large eye height.

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A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels

Cited by 10 publications

References 13 publications

41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology

41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology

Compact Models for Simulation of On-Chip ESD Protection Networks

A Mueller-Müller CDR with False-Lock-Aware Locking Scheme for a 56-Gb/s ADC-Based PAM4 Transceiver

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