APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems 2008
DOI: 10.1109/apccas.2008.4746254
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A 1.2V 5.14mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4GHz ZigBee applications

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Cited by 7 publications
(2 citation statements)
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“…After the SCL latches, two inverters reconstruct the logical levels, control the load matching and provide isolation. With a custom optimized design and dedicated layout, this topology has proven applica- bility for low-power design in current deep-submicrometer technologies [4]. However, the topology could be very sensitive to the VCO oscillation amplitude variations when temperature increases.…”
Section: Classical Lc-vco With Constant Biasmentioning
confidence: 99%
“…After the SCL latches, two inverters reconstruct the logical levels, control the load matching and provide isolation. With a custom optimized design and dedicated layout, this topology has proven applica- bility for low-power design in current deep-submicrometer technologies [4]. However, the topology could be very sensitive to the VCO oscillation amplitude variations when temperature increases.…”
Section: Classical Lc-vco With Constant Biasmentioning
confidence: 99%
“…The Quality factor is increased with multi-metal layer inductor, which reduces DC resistance and HRS reduces substrate effect at 5GHz tuned oscillator. In paper [ [5]], LC tank is used with complementary cross coupled negative resistance, which is tail biased with NMOS current mirror course. Symmetrical inductor and PMOS varactors in inversion mode are used for fine tuning and metalmetal capacitor array is used for additional coarse tuning for process variation changes, which is controlled by 3-bit signal.…”
Section: Introductionmentioning
confidence: 99%