A 1.25-GHz Fully Integrated DC–DC Converter Using Electromagnetically Coupled Class-D <i>LC</i> Oscillators

Novello, Alessandro; Atzeni, Gabriele; Kunzli, Jonas; Cristiano, Giorgio; Coustans, Mathieu; Jang, Taekwang

doi:10.1109/jssc.2021.3112129

Cited by 8 publications

(10 citation statements)

References 47 publications

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“…6. From this visualization, we can conclude that our structure [2] achieved higher FoM than the other works realized in standard CMOS technology [30]. Moreover, the FoM evaluation shows that the developed inductor structure is better than some structures fabricated in more complex advanced technologies (e.g.…”

Section: Figure Of Meritmentioning

confidence: 65%

An Overview of Fully On-Chip Inductors

Ondica¹,

Kovac²,

Hudec³

et al. 2023

RADIOENGINEERING

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This paper focuses on full integration of passive devices, especially inductors with emphasis on multi-layer stacked (MLS) structures of fully integrated inductors using patterned ground shield (PGS) and fully integrated capacitor. Comparison of different structures is focused on the main electrical parameters of integrated inductors (e.g. inductance 𝐿, inductance density 𝐿 𝐴 , quality factor 𝑄, frequency of maximum quality factor 𝐹 𝑄max , self-resonant frequency FSR, and series resistance 𝑅 DC ) and other non-electrical parameters (e.g. required area, manufacturing process, purpose, etc.) that are equally important during comparison of the structures. Categorization of inductor structures with most significant results that was reported in the last years is proposed according to manufacturing process. Final geometrical and electrical properties of the structure in great manner accounts to the fabrication process of integrated passive device. This work offers an overview and state-of-the-art of the integrated inductors as well as manufacturing processes used for their fabrication. Second purpose of this paper is insertion of the proposed structure from our previous work among the other results reported in the last 7 years. With the proposed solution, one can obtain the highest inductance density 𝐿 𝐴 = 23.59 nH/mm 2 and second highest quality factor 𝑄 = 10.09 amongst similar solutions reported in standard technologies that is also suitable competition for integrated inductors manufactured in advanced technology nodes.

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Section: Figure Of Meritmentioning

confidence: 65%

An Overview of Fully On-Chip Inductors

Ondica¹,

Kovac²,

Hudec³

et al. 2023

RADIOENGINEERING

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“…Hence, adjusting the transistor width achieves an identical onresistance ron for both PMOS and NMOS [10]. Furthermore, the work [5] presented a duty-cycling scheme with dynamic load current using two NMOS footer transistors to minimize the power loss at various loads (i.e. light or heavy) by alternately activating and deactivating the oscillators.…”

Section: B Power Losses Reduction and Optimizationmentioning

confidence: 99%

“…The transistor sizing optimization is essential to reduce the conduction loss by the on-resistance of the cross-coupled switch. The switching loss is negligible when the switching frequency of the footer transistor is lower than the resonant frequency [5]. Also, appropriate sizing of PMOS and NMOS alleviates the tradeoff between switching and conduction loss at a ratio of 2:1 [43].…”

Section: B Power Losses Reduction and Optimizationmentioning

confidence: 99%

“…The key performance index in the power converter design consists three major parameters, which is the efficiency, transient response, and power density [3]. In compromise of performance tradeoffs, fully-integrated dc-dc converter plays a vital role in SoC with a small form factor in providing a regulated voltage for point-of-load application [4], [5]. Among the dc-dc converter architectures, hybrid dc-dc converter topology shows superior balance in high efficiency and power density with an optimized tradeoff in favorable degree among the linear and switching topology.…”

Section: Introductionmentioning

confidence: 99%

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Design and Implementation of Hybrid DC-DC Converter: A Review

et al. 2023

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The advancement in Power Management Integrated Circuit (PMIC) has driven the DC-DC conversion technology into a System-on-Chip (SoC) solutions, leveraging CMOS technology scaling from 180nm to 22nm and on-chip passive element integration. Concurrently, as the applications demand smaller form factor solution towards device portability with optimized power qualities, switched-capacitor-inductor hybrid architectures with fully-integrated passives have become a popular choice for a compact and high efficiency converter solution, in contrast to bulky and discrete component based alternatives. This article reviews the latest advancements in hybrid dc-dc topologies, specifically for low-power applications to address the downsides such as charge sharing loss, high current ripple, limited conversion ratio, low power density and efficiency. An overview of capacitor and inductor technology is discussed in terms of on-chip parasitic losses, and miniaturization. A comprehensive comparison in the state-of-the-art hybrid dc-dc converter work is tabulated with power density and efficiency as the primary performance metrics, highlighting their operability in low-power applications. Moreover, a discussion is included with quantified benchmarks to justify the viability of converters, along with the future recommendation of realizing ultra-high switching frequency for smaller footprint inductor and design approach to resolve the current tradeoff bottlenecks.

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“…On this topic, ref. [45] presents a fully integrated dc-dc converter topology based on electromagnetically coupled class-D LC oscillators that enable up to 2.5 GHz switching frequency, allowing aggressive scaling of the on-chip passives. Ref.…”

Section: Related Workmentioning

confidence: 99%

A Self-Powered and Battery-Free Vibrational Energy to Time Converter for Wireless Vibration Monitoring

Panayanthatta

Clementi

Ouhabaz

et al. 2021

Sensors

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Wireless sensor nodes (WSNs) are the fundamental part of an Internet of Things (IoT) system for detecting and transmitting data to a master node for processing. Several research studies reveal that one of the disadvantages of conventional, battery-powered WSNs, however, is that they typically require periodic maintenance. This paper aims to contribute to existing research studies on this issue by exploring a new energy-autonomous and battery-free WSN concept for monitor vibrations. The node is self-powered from the conversion of ambient mechanical vibration energy into electrical energy through a piezoelectric transducer implemented with lead-free lithium niobate piezoelectric material to also explore solutions that go towards a greener and more sustainable IoT. Instead of implementing any particular sensors, the vibration measurement system exploits the proportionality between the mechanical power generated by a piezoelectric transducer and the time taken to store it as electrical energy in a capacitor. This helps reduce the component count with respect to conventional WSNs, as well as energy consumption and production costs, while optimizing the overall node size and weight. The readout is therefore a function of the time it takes for the energy storage capacitor to charge between two constant voltage levels. The result of this work is a system that includes a specially designed lead-free piezoelectric vibrational transducer and a battery-less sensor platform with Bluetooth low energy (BLE) connectivity. The system can harvest energy in the acceleration range [0.5 g–1.2 g] and measure vibrations with a limit of detection (LoD) of 0.6 g.

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A 1.25-GHz Fully Integrated DC–DC Converter Using Electromagnetically Coupled Class-D LC Oscillators

Cited by 8 publications

References 47 publications

An Overview of Fully On-Chip Inductors

An Overview of Fully On-Chip Inductors

Design and Implementation of Hybrid DC-DC Converter: A Review

A Self-Powered and Battery-Free Vibrational Energy to Time Converter for Wireless Vibration Monitoring

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