“…3, for controlling the transmitted optical power of the laser diode, this work uses an analog circuit technique based on conventional feedback, which is composed of a high-speed transimpedance amplifier (TIA) and top hold/bottom hold (TH/BH) peak detection circuits. This is in contrast to many previous works [6]- [8] for the burst-mode transmitter that have been implemented using digital APC circuits.…”
Section: Transmitter Architecture and Circuitsmentioning
This brief presents a CMOS burst-mode optical transmitter suitable for use in 1.25-Gb/s Ethernet passive optical network applications. Based on feedback from the monitoring photodiode, in order to control consecutive burst data the proposed transmitter in this brief uses a reset mechanism, which allows fast responses from the beginning of a high-speed input burst. The chip is fabricated in mixed-mode 0.18-m CMOS technology and measurements are implemented in a chip-on-board configuration using a pig-tailed type Fabry-Perot laser. Under burst-mode operation of 1.25-Gb/s pseudorandom binary sequences, measurements show about 1-dBm averaged transmitted optical power with an over 12-dB extinction ratio over a wide temperature range.Index Terms-Burst mode, Ethernet passive optical network (E-PON), gigabit Ethernet, laser driver, optical transmitter.
“…3, for controlling the transmitted optical power of the laser diode, this work uses an analog circuit technique based on conventional feedback, which is composed of a high-speed transimpedance amplifier (TIA) and top hold/bottom hold (TH/BH) peak detection circuits. This is in contrast to many previous works [6]- [8] for the burst-mode transmitter that have been implemented using digital APC circuits.…”
Section: Transmitter Architecture and Circuitsmentioning
This brief presents a CMOS burst-mode optical transmitter suitable for use in 1.25-Gb/s Ethernet passive optical network applications. Based on feedback from the monitoring photodiode, in order to control consecutive burst data the proposed transmitter in this brief uses a reset mechanism, which allows fast responses from the beginning of a high-speed input burst. The chip is fabricated in mixed-mode 0.18-m CMOS technology and measurements are implemented in a chip-on-board configuration using a pig-tailed type Fabry-Perot laser. Under burst-mode operation of 1.25-Gb/s pseudorandom binary sequences, measurements show about 1-dBm averaged transmitted optical power with an over 12-dB extinction ratio over a wide temperature range.Index Terms-Burst mode, Ethernet passive optical network (E-PON), gigabit Ethernet, laser driver, optical transmitter.
“…11 gives the sensitivity of a 1.25-Gb/s BMRx as a function of G with σ IN,T measured as 250 nA rms together with the results from [12]. Such a BMRx can be used for the upstream transmission over GPONs [11]. With G = 6 and σ β equal to 0.05, a sensitivity of −29 dBm is reached for 99.7% of all BMRx samples.…”
Section: Resultsmentioning
confidence: 98%
“…The adoption of the ITU-T G.984.2 standard [5] [so-called gigabit-capable passive optical network (GPON)] and the IEEE 802.3ah standard {so-called gigabit-capable Ethernet passive optical network [(G)EPON]} [6] has intensified the research aimed at developing gigabit-capable BMRxs, with an emphasis on achieving high sensitivity and dynamic range [7]- [11]. Indeed, successful and economical deployment of PONs requires large physical reach (distance between the subscriber and the central office) and especially large splitting factors (the number of subscribers served by a single PON) [12].…”
Abstract-This paper presents the influence of random direct current (dc) offsets on the sensitivity of dc-coupled burst-mode receivers (BMRxs). It is well known that a BMRx exhibits a noisy decision threshold, resulting in a sensitivity penalty. If the BMRx is dc coupled, an additional penalty is incurred by random dc offsets. This penalty can only be determined for a statistically significant number of fabricated BMRx samples. Using Monte Carlo (MC) simulations and a detailed BMRx model, the relationship between the variance of this random dc offset, the resulting sensitivity penalty, and BMRx yield (the fraction of fabricated BMRx samples that meets a given sensitivity specification) is evaluated as a function of various receiver parameters. The obtained curves can be used to trade off BMRx die area against sensitivity for a given yield. It is demonstrated that a thorough understanding of the relationship between BMRx sensitivity, BMRx yield, and the variance of the random dc offsets is needed to optimize a dccoupled BMRx with respect to sensitivity and die area for a given yield. It is shown that compensation of dc offsets with a resolution of 8 bits results in a sensitivity penalty of 1 dB for a wide range of random dc offsets.Index Terms-Avalanche photodiodes, bit error rate (BER), burst-mode receiver (BMRx), optical access network, optical receiver.
“…In this way the BM-RX dynamic range can be dramatically improved. Five circuit techniques [32] have been proposed for AOC/ATC: 1) reduction of AC coupling capacitance, 2) feed-forward top/bottom (positive/negative) peak detect with Reset [14] and [36]- [39], 3) edge detect without Reset [40], 4) feed-forward average detect without Reset [35] and [41], 5) feedback AOC without Reset [42]. A newly developed feedback AOC with switchable loop BW and on-chip Reset generation is reported in [43]- [45].…”
Abstract-This paper gives a tutorial overview on high speed burst-mode receiver (BM-RX) requirements, specific for time division multiplexing passive optical networks (TDM-PONs), and design issues of such BM-RXs as well as their advanced design techniques. It focuses on how to design BM-RXs with short burst overhead for fast synchronization. We present design principles and circuit architectures of various types of burst-mode transimpedance amplifiers (BM-TIAs), burst-mode limiting amplifiers (BM-LAs) and burst-mode clock and data recovery (BM-CDR) circuits. The recent development of 10Gb/s BM-RXs is highlighted also including dual-rate operation for coexistence with deployed PONs and on-chip auto reset generation to eliminate external timing-critical control signals provided by a PON medium access control (MAC). Finally sub-system integration and state-of-the-art system performance for 10Gb/s PONs are reviewed. Copyright (c) 2013 IEEE. Personal use of this material is permitted. However, permission to use this material for any other purposes must be obtained from the IEEE by sending a request to pubs-permissions@ieee.org. and electronics engineers (IEEE) respectively. Both ongoing standardization efforts were endorsed by the concurrent development of innovative upstream (US) burst-mode receivers (BM-RXs), the physical media dependent (PMD) keystone component of any PON system. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.
Index Terms-
> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 2higher aggregate rates of 40G are achieved by time/wavelength division multiplexing (TWDM). 40Gb/s TDM line rates are beyond NG-PON2. This paper presents a tutorial overview of various BM-RX design techniques for both ITU-T and IEEE TDM-PONs, and their recent developments focusing on how to achieve fast RX synchronization and overall good performance. Section II describes the specific requirements of the BM-RXs from a system level point of view in terms of optical power budget, burst overhead (OH) composition for synchronization, and the overall BM-RX figure of merit. Section III discusses two typical RX coupling methods of alternating current (AC)-coupling and direct current (DC)-coupling. Their intrinsically associated technical issues and some solutions are introduced. Section IV presents various 2R BM-RXs design techniques in detail from a component development point of view. Focusing on 10Gb/s operation different configurations and design approaches of burst-mode transimpedance amplifiers (BM-TIAs) and burst-mode limiting amplifiers (BM-LAs) are reviewed and compared. 10Gb/s burst-mode clock-data recovery (BM-CDR) design techniques are separately described in Section V. Furthermore 10G/1Gb/s dual-rate BM-RX requirements and their implementations are presented in Section VI. Afterwards state-of-the-art 10Gb/s BM-RX prototypes and their sub-system performance are demonstrated i...
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