A 1.248–2.918 Gb/s low-power transmitter for MIPI M-PHY with 2-step impedance calibration loop in 0.11 μm CMOS

Kim, SangYun; Lee, Juri; Oh, Seong-Jin; Kim, InSeong; Park, Young-Jun; Tiwari, Honey Durga; Park, Hyung-Gu; Pu, YoungGun; Hwang, Keum Cheol; Yang, Youngoo; Seo, Munkyo; Lee, Kang-Yoon

doi:10.1007/s10470-015-0516-0

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Low-power High-speed Voltage-mode Drivers1

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Cited by 2 publications

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“…A common circuit topology for high-speed low-power differential transmitters is depicted in Figure 1; a similar topology is presented in [2]. A voltage-mode output driver (H-bridge) is supplied by a low-dropout voltage regulator (LDO) and driven by a Pre-Driver stage.…”

Section: Low-power High-speed Voltage-mode Driversmentioning

confidence: 99%

Enhanced macromodels of high-speed low-power differential drivers

Signorini

Siviero

Stievano

et al. 2016

2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)

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Section: Low-power High-speed Voltage-mode Driversmentioning

confidence: 99%

Enhanced macromodels of high-speed low-power differential drivers

Signorini

Siviero

Stievano

et al. 2016

2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)

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Enhanced macromodels of high-speed low-power differential drivers

Signorini

Siviero

Stievano

et al. 2015

2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)

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High-speed differential interfaces implementing specific solutions for low-power consumption and low-EMI disturbances are vastly used in mobile platforms. In these devices, the slew rate is suitably controlled, the communication scheme alternates data-bursts followed by power-saving states, the voltage swing and the common-mode level are reduced. To achieve these targets, a key role in voltage-mode output drivers is played by an internal voltage-regulator. The latter exhibits a rich dynamic behavior, with non-negligible effects on the transmitter outputs, that need to be carefully characterized. In this paper, a modeling strategy based on a few key enhancements of state-of-the-art solutions is presented, leading to compact and accurate models. The feasibility and strengths of the proposed approach are verified on a low-power high-speed voltage-mode driver.

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A 1.248–2.918 Gb/s low-power transmitter for MIPI M-PHY with 2-step impedance calibration loop in 0.11 μm CMOS

Cited by 2 publications

References 10 publications

Enhanced macromodels of high-speed low-power differential drivers

Enhanced macromodels of high-speed low-power differential drivers

Enhanced macromodels of high-speed low-power differential drivers

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