A 1.2 V 285&amp;#x03BC;A analog front end chip for a digital hearing aid in 0.13 &amp;#x03BC;m CMOS

Sukumaran, Amrith; Karanjkar, Kunal; Jhanwar, Sandeep; Krishnapura, Nagendra; Pavan, Shanthi

doi:10.1109/asscc.2013.6691066

Cited by 9 publications

(6 citation statements)

References 7 publications

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“…Figure 2a shows an inverting amplifier with resistive feedback [3][4][5][6]. The gain of the amplifier is set by the ratio of resistors R 1 and R 2 (G = −R 2 /R 1 ) and the input impedance of it is R 1 .…”

Section: Resistive Feedback Architecturementioning

confidence: 99%

“…However, the small amplitude of the microphone's output signals, and the uncertain dc level of the output make it unpractical for a microphone to drive ADCs directly. Therefore, a preamplifier is usually used in an M-ROIC to handle such obstacle [3][4][5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

“…For example, inverting an amplifier with resistive feedback can achieve over 100 dB dynamic range (DR). However, the required noise level for the SNR limits the input impedance of the preamplifier, which leads to effective gain reduction [3][4][5][6]. Moreover, typical resistive feedback architectures 2.…”

Section: Introductionmentioning

confidence: 99%

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Analysis and Design of a Microphone Preamplifier for Mobile Applications

Park

2021

Electronics

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A design of an on-chip ac-coupling preamplifier for mobile applications is presented. A microphone preamplifier should have a large input impedance to mitigate the effective-gain reduction caused by the microphone’s non-zero output impedance. From a review of previously reported microphone preamplifier structures in terms of input impedance, feasibility of on-chip ac-coupling, and noise performance, we chose an inverting amplifier structure with capacitive feedback. In addition, to provide dc bias path, we used off-state MOSFET switches as pseudo-resistors of very large resistance in the giga-ohm range. The large resistance enables on-chip ac-coupling with sufficient noise performance. A fast start-up is achieved by turning-on the switch for a short period during the preamplifier start-up. The gain of the preamplifier can be programmed from 0 dB to 21 dB with 3 dB steps. A 2-stage pseudo-class-AB amplifier was adopted to reduce power consumption. The proposed preamplifier was implemented using a 28 nm CMOS process and achieves 107 dB dynamic range in a 20 kHz bandwidth under 0 dB gain setting and balanced differential input signal. The preamplifier dissipates a power of 270 μW with a 1.8 V supply.

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Section: Resistive Feedback Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Analysis and Design of a Microphone Preamplifier for Mobile Applications

Park

2021

Electronics

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“…Under low voltage supply such as 1 V, the OTA design is always a great challenge [10][11][12][13]. In this paper, the OTA circuit is as shown in Figure 4.…”

Section: Circuit Designmentioning

confidence: 99%

“…Also, the input PMOS transistors can minimize the equal input noise due to its low flick noise, which means for the same output amplitude level the SNR is improved [6][7][8][9][10]. In the second stage, Class-AB composition optimizes the output quiescent current, while achieving a larger output swing.…”

Section: Vlsi Designmentioning

confidence: 99%

A 69-dB SNR 89-μW AGC for Multifrequency Signal Processing Based on Peak-Statistical Algorithm and Judgment Logic

Dai

Chen

2016

VLSI Design

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A novel peak-statistical algorithm and judgment logic (PSJ) for multifrequency signal application of Autogain Control Loop (AGC) in hearing aid SoC is proposed in this paper. Under a condition of multifrequency signal, it tracks the amplitude change and makes statistical data of them. Finally, the judgment is decided and the circuit gain is controlled precisely. The AGC circuit is implemented with 0.13 μm 1P8M CMOS mixed-signal technology. Meanwhile, the low-power circuit topology and noise-optimizing technique are adopted to improve the signal-to-noise ratio (SNR) of our circuit. Under 1 V voltage supply, the peak SNR achieves 69.2 dB and total harmonic distortion (THD) is 65.3 dB with 89 μW power consumption.

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A Low Power, High Performance Analog Front-End Circuit for 1 V Digital Hearing Aid SoC

Chen

Fan

et al. 2014

Circuits Syst Signal Process

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A 1.2 V 285μA analog front end chip for a digital hearing aid in 0.13 μm CMOS

Cited by 9 publications

References 7 publications

Analysis and Design of a Microphone Preamplifier for Mobile Applications

Analysis and Design of a Microphone Preamplifier for Mobile Applications

A 69-dB SNR 89-μW AGC for Multifrequency Signal Processing Based on Peak-Statistical Algorithm and Judgment Logic

A Low Power, High Performance Analog Front-End Circuit for 1 V Digital Hearing Aid SoC

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