A 0.8 V asynchronous ADC for energy constrained sensing applications

Trakimas, Michael; Sonkusale, Sameer

doi:10.1109/cicc.2008.4672051

Cited by 25 publications

(8 citation statements)

References 7 publications

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“…To reduce DC power that is often dissipated by analog bias current, clocked comparator [2][9][10] [15] is desirable and used in this work. The 8-bit SAR ADC, which is an extension of Fig.…”

Section: Methodsmentioning

confidence: 99%

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Signal-dependent analog-to-digital converter based on MINIMAX sampling

Homjakovs

Hashimoto

Onoye

et al. 2012

2012 International SoC Design Conference (ISOCC)

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Abstract-This paper presents a physical implementation of a signal-dependent analog-to-digital converter (ADC), called MINIMAX ADC. This ADC captures a sample every time an analog signal reaches its local maximum or minimum value. In this ADC, sampling naturally adapts to input signal frequency, which enables high data compression rate and power reduction to be achieved. A 8-bit MINIMAX ADC was implemented in 180nm CMOS technology. Measurement results show that the proposed MINIMAX ADC consumes lower power for less active signals, and the power reduction from conventional synchronous ADC is up to 20%.

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“…To reduce DC power that is often dissipated by analog bias current, clocked comparator [2][9][10] [15] is desirable and used in this work. The 8-bit SAR ADC, which is an extension of Fig.…”

Section: Methodsmentioning

confidence: 99%

“…As a result, non-uniformly spaced samples, whose local sampling density depends on the signal local properties, are obtained. This scheme requires at least two constantly operating comparators and two reference voltage circuits, which contributes to power consumption [2].…”

Section: Introductionmentioning

confidence: 99%

Signal-dependent analog-to-digital converter based on MINIMAX sampling

Homjakovs

Hashimoto

Onoye

et al. 2012

2012 International SoC Design Conference (ISOCC)

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“…Several ADCs for level crossing sampling have been presented [17], [19], [20]; some of these [19] use quantized time, but can be adapted to CT operation [21], [22].…”

Section: E Encodingmentioning

confidence: 99%

Event-driven, continuous-time ADCs and DSPs for adapting power dissipation to signal activity

Tsividis

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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“…A capacitive DAC structure based on charge sharing principle was used in [9] which generate the varying comparison interval. A hybrid switched-capacitor/resistor-string architecture was used for implementing DAC in [10] [12]. The 2 DACs used in this architecture create the threshold levels which bound the input signal from above and below.…”

Section: Previous Literaturementioning

confidence: 99%

Design of an Asynchronous 1 Bit Charge Sharing Digital to Analog Converter for a Level Crossing ADC

Antony¹

2018

IJRASET

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This paper presents the design of a charge sharing 1 bit DAC with pseudo resistors suitable for an asynchronous level crossing ADC. Dummy NMOS devices are added to the 1 bit DAC for reducing the charge accumulation and clock feed through giving a 81.26 % increase in SFDR for 5 kHz input frequency compared to the 1 bit DAC with only pseudo resistors. The asynchronous control logic for the DAC is designed digitally and optimized for lower power consumption. The DAC and its control logic has been designed using 180nm technology in cadence using a supply voltage of 0.8 V and consumes an average power of 2.323 nW. Keyword: Digital to Analog Converters (DAC), Analog to Digital Converters (ADC), Asynchronous, Level crossing, pseudo resistors I. INTRODUCTIONAsynchronous ADC architectures are emerging as an excellent alternative for replacing synchronous ADCs in various applications such as portable and implantable biomedical signal sensing devices, remote environmental monitors and sensors, military applications, magnetic disk reader, optical disk readers and wireless applications such as audio devices and cellular telephones. The advantages of asynchronous circuits compared to their synchronous counter parts are higher speed, lower power consumption, and smaller area, immunity to metastable behaviour, less clock skew and low susceptibility to electromagnetic interference. Level crossings ADCs are asynchronous ADCs that generate output samples only when the input signal crosses a threshold level [1]. Level crossing ADCs offers lower sampling rate, power consumption and area than synchronous ADCs. Level crossing ADC has been mainly used in embedded sensing systems, such as environmental sensors (temperature, pressure sensors), implantable biomedical applications, hearing aids and ultrasound applications [2]- [7], [10],[ 11]. This paper presents the design of a charge sharing 1 bit DAC with pseudo resistors and additional dummy NMOS devices for a level crossing ADC. A digital DAC logic using gates and latches for the control of the 1 bit DAC asynchronously is also designed in this paper. In this paper, section II discusses previous literatures on DAC used in level crossing ADCs. Section III gives the circuit implementation followed by results and discussion in section IV. Section V gives the conclusion of the paper.

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A 0.8 V asynchronous ADC for energy constrained sensing applications

Cited by 25 publications

References 7 publications

Signal-dependent analog-to-digital converter based on MINIMAX sampling

Signal-dependent analog-to-digital converter based on MINIMAX sampling

Event-driven, continuous-time ADCs and DSPs for adapting power dissipation to signal activity

Design of an Asynchronous 1 Bit Charge Sharing Digital to Analog Converter for a Level Crossing ADC

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