A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder

Sze, Vivienne; Finchelstein, D.F.; Sinangil, Mahmut E.; Chandrakasan, Anantha P.

doi:10.1109/jssc.2009.2028933

Cited by 45 publications

(21 citation statements)

References 22 publications

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“…Note that the external bus power dissipation is directly proportional to the total number of bit-toggles per transition [44]. This enormous amount of data results in high latency and energy consumption (around 40% of the total system energy is consumed by the external IO [43] [22]). Therefore, saving external memory accesses becomes vital for reducing the energy consumption of a video encoding system.…”

Section: Fig 4 Block Matching Memory Access Comparison Between Hevc mentioning

confidence: 99%

AMBER: Adaptive energy management for on-chip hybrid video memories

Khan

Shafique

Henkel

2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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The ever increasing leakage power of memories in a system has motivated researches for exploiting unconventional memory architectures. Non-Volatile Memory (NVM) used in conjunction with the conventional on-chip SRAMs has given birth to the hybrid memory paradigm, which can be intelligently exploited to reduce the energy consumption while tackling the high read and write latencies of NVMs. We present a novel scheme AMBER that aims at minimizing the total memory energy consumption of a video processing system by leveraging the application-specific properties and distinct latency and power properties of different memory types. AMBER also features architectural support for data-fetching from external memory and adaptively filling the different on-chip memories. We employ AMBER in the next-generation High Efficiency Video Coding (HEVC) standard to minimize the energy consumption of the new complex motion prediction process. Experimental results demonstrate that our AMBER scheme achieves significant energy savings (average 43%) for the on-chip memory.

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Section: Fig 4 Block Matching Memory Access Comparison Between Hevc mentioning

confidence: 99%

AMBER: Adaptive energy management for on-chip hybrid video memories

Khan

Shafique

Henkel

2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…In hardware implementation, various simplifications are often considered and implemented [2,3]. For example, search algorithm are designed to allow search ranges and cost calculations to be shared across different block sizes to reduce hardware complexity [4,5].…”

Section: Hevc Motion Estimation Architecturementioning

confidence: 99%

Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine

Sinangil

Chandrakasan

Sze

et al. 2012

2012 19th IEEE International Conference on Image Processing

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This paper presents a comparison between various High Efficiency Video Coding (HEVC) motion estimation configurations in terms of coding efficiency and memory cost in hardware. An HEVC motion estimation hardware model that is suitable to implement HEVC reference software (HM) search algorithm is created and memory area and data bandwidth requirements are calculated based on this model. 11 different motion estimation configurations are considered. Supporting smaller block sizes is shown to impose significant memory cost in hardware although the coding gain achieved through supporting them is relatively smaller. Hence, depending on target encoder specifications, the decision can be made not to support certain block sizes. Specifically, supporting only 64x64, 32x32 and 16x16 block sizes provide 3.2X on-chip memory area, 26X on-chip bandwidth and 12.5X off-chip bandwidth savings at the expense of 12% bit-rate increase when compared to the anchor configuration supporting all block sizes.

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“…Manuscript Much of the applicable research has focused on the reduction of power consumption in the video codec itself; such research has shown good results. Sze et al [4] implemented a full real-time 720p H.264 decoder in 65 nm by using a variety of techniques such as multiple voltage, frequency domains, frame level dynamic voltage, and frequency scaling. In this study, the core power consumption of the video decoder was reduced to 1.8 mW.…”

Section: Introductionmentioning

confidence: 99%

Low-Power Motion Estimation Processor with 3D Stacked Memory

Zhang

Zhou

Goto

2015

IEICE Trans. Fundamentals

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Motion estimation (ME) is a key encoding component of almost all modern video coding standards. ME contributes significantly to video coding efficiency, but, it also consumes the most power of any component in a video encoder. In this paper, an ME processor with 3D stacked memory architecture is proposed to reduce memory and core power consumption. First, a memory die is designed and stacked with ME die. By adding face-to-face (F2F) pads and through-silicon-via (TSV) definitions, 2D electronic design automation (EDA) tools can be extended to support the proposed 3D stacking architecture. Moreover, a special memory controller is applied to control data transmission and timing between the memory die and the ME processor die. Finally, a 3D physical design is completed for the entire system. This design includes TSV/F2F placement, floor plan optimization, and power network generation. Compared to 2D technology, the number of input/output (IO) pins is reduced by 77%. After optimizing the floor plan of the processor die and memory die, the routing wire lengths are reduced by 13.4% and 50%, respectively. The stacking static random access memory contributes the most power reduction in this work. The simulation results show that the design can support real-time 720p @ 60 fps encoding at 8 MHz using less than 65 mW in power, which is much better compared to the state-of-the-art ME processor. key words: 3DIC design, motion estimation processor, low power design, memory stacking

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A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder

Cited by 45 publications

References 22 publications

AMBER: Adaptive energy management for on-chip hybrid video memories

AMBER: Adaptive energy management for on-chip hybrid video memories

Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine

Low-Power Motion Estimation Processor with 3D Stacked Memory

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