A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs

Chen, Yen Huei; Chan, Gary; Chou, Shao Yu; Pan, Hsien-Yu; Wu, J. J.; Lee, R.; Liao, H.J.; Yamauchi, Hiroyuki

doi:10.1109/jssc.2009.2014208

Cited by 21 publications

(7 citation statements)

References 8 publications

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“…However, in contrast to the processor, the SRAM has a lowbounded supply voltage requirement to meet the target yield [5]- [7]. This limitation has worsened in FinFET technology because the voltage difference between the supply voltage and threshold voltage (V th ) has decreased due to technology scaling [8].…”

Section: Introductionmentioning

confidence: 99%

“…A dual-rail architecture concept was suggested in [8], [10], and [11] for meeting the supply voltage requirement of SRAM. In the dual-rail architecture, the processor operates with a low supply voltage (VDDL), while the SRAM operates with a high supply voltage (VDDH).…”

Section: Introductionmentioning

confidence: 99%

“…In this way, the total power consumed by the entire chip can be reduced while maintaining the target yield of the SRAM. Another solution is to adopt the dual-rail architecture inside the SRAM, which is called dual-rail SRAM [8]- [11]. The energy efficiency of the dual-rail SRAM can be optimized by appropriately distributing the VDDH and VDDL to the cell array, peripheral circuits, and control block in the SRAM.…”

Section: Introductionmentioning

confidence: 99%

“…The energy efficiency of the dual-rail SRAM can be optimized by appropriately distributing the VDDH and VDDL to the cell array, peripheral circuits, and control block in the SRAM. Several dual-rail SRAM schemes were introduced in [8]- [12].…”

Section: Introductionmentioning

confidence: 99%

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An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache

et al. 2020

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An embedded level-shifting (ELS) dual-rail SRAM is proposed to enhance the availability of dual-rail SRAMs. Although dual-rail SRAM is a powerful solution for satisfying the increasing demand for low-power applications, the enormous performance degradation at low supply voltages cannot meet the high-performance cache requirement in recent computing systems. The requirement of many level shifters is another drawback of the dual-rail SRAM because it degrades the energy-savings. The proposed ELS dualrail SRAM achieves energy-savings by using a low supply voltage to precharge bitlines while minimizing the performance overhead by appropriately assigning a high-supply voltage to critical circuit blocks with effective level-shifting circuits. The sense amplifier embeds a level-shifting operation, thereby operating with a high supply voltage for a fast sensing operation. The proposed dynamic output buffer resolves the potential static current problem and improves the read delay. The number of level shifters is reduced using a proposed write driver, which conducts level-shifting and write-driving simultaneously. The proposed ELS dual-rail SRAM achieves low-power operation with 71.4% power consumption compared to single-rail SRAM with 72% performance overhead in circuit-level simulation, while the previous hybrid dual-rail SRAM shows 67.8% energy consumption with 270% performance overhead. In architecture-level simulation using Gem5 simulator with SPEC2006 benchmarks, the system with the ELS dual-rail SRAM caches shows, on average, 29% performance improvement compared to that of the system with the hybrid dual-rail SRAM caches.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache

et al. 2020

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“…DARKMEM, our approach for reducing the PLM static power, is based on three main observations. First, SRAM memories are increasingly fabricated with the possibility of selectively turning off the peripheral circuitry (to be kept active only when effectively accessing the data) or also the memory cells (to be kept active to retain the data) [5]. These dual-rail SRAMs have been used in processors [14], GPUs [23], or applicationspecific systems [20] with only two additional sleep transistors between each SRAM bank and the ground [19].…”

Section: Introductionmentioning

confidence: 99%

DarkMem: Fine-grained power management of local memories for accelerators in embedded systems

Pilato¹,

Carloni²

2018

2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)

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SRAM consumes a growing fraction of the static power in heterogeneous SoCs, as embedded memories take 70% to 90% of the area of specialized accelerators. We present DARK-MEM as a comprehensive solution for fine-grained power management of accelerator local memories. The DARKMEM methodology optimizes at design time the bank configuration for each given accelerator to maximize power-gating opportunities. The DARK-MEM microarchitecture dynamically varies the operating mode of each memory bank according to the accelerator workload. In our experiments, DARKMEM reduces the SRAM static power by more than 40% on average, which translates into a reduction of the total power by almost 18% on average with less than 1% overhead.

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Variation-Tolerant SRAM Write and Read Assist Techniques

Abu-Rahma

Anis

2012

Nanometer Variation-Tolerant SRAM

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A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs

Cited by 21 publications

References 8 publications

An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache

An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache

DarkMem: Fine-grained power management of local memories for accelerators in embedded systems

Variation-Tolerant SRAM Write and Read Assist Techniques

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