A 0.5V 200MHz offset trimmable latch comparator in standard 0.18um CMOS process

Mohammadi, Meysam; Sadeghipour, Khosrov Dabbagh

doi:10.1109/iraniancee.2013.6599863

Cited by 4 publications

(2 citation statements)

References 6 publications

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“…The offset calibration method proposed in [22] compensates the inputreferred offset voltage by trimming the effective transconductance of the second-stage PMOS input pairs, while the degradation of the speed, noise, and power efficiency caused by the calibration circuits is less than 0.72%. A new offset trimmable comparator and a speed-up technique were presented in [23]. The body terminal of PMOS transistors was utilized as an input terminal to achieve rail-to-rail input range and meet the requirement of low-voltage applications.…”

Section: Introductionmentioning

confidence: 99%

Design of Self-Calibration Comparator for 12-Bit SAR ADCs

Tang

Wang

et al. 2023

Electronics

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A novel self-calibration comparator for a 12-bit 2.5 MSPS successive approximation register analog-to-digital converter (SAR ADC) applied in a touch microcontroller unit (MCU) with small area, high precision, fast response speed, and low-voltage detection is proposed in this paper. A combination of input/output offset storage (IOS/OOS) and an offset trimming circuit was employed to reduce the offset of the cascade preamplifier and the operational transconductance amplifier (OTA), a novel offset trimming circuit with a 5-bit digital controller was designed to further reduce the residual offset voltage, and an improved self-calibration technology was also implemented to compensate the conversion error in SAR ADC system to a minimum. Simulation and measured results show that the input-referred offset calibrating range is ±9.15 mV at 0.61 mV/step, the low-voltage detection of SAR ADC is realized by compensating the conversion error to a minimum, and the effective number of bits (ENOB) and figure of merit (FoM) at 5 V supply and 2.5 M/s rate in the 12-bit SAR ADC with a 95 nm CMOS are 11.33 bits and 726.6 fJ/conversion-step, respectively. The proposed self-calibration comparator applied in the SAR ADC system can automatically eliminate the offset voltage caused by nonidealities and meet the requirements of the touch MCU.

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Section: Introductionmentioning

confidence: 99%

Design of Self-Calibration Comparator for 12-Bit SAR ADCs

Tang

Wang

et al. 2023

Electronics

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“…Dynamic comparators with low supply voltage are presented in [1] and [2]. They need clock signals to reset the outputs.…”

Section: Introductionmentioning

confidence: 99%

A sub-nW mV-range programmable threshold comparator for near-zero-energy sensing

Wang

Waters

Shi

2016

2016 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper describes a comparator capable of detecting mV-range input voltage signals reliably using sub-nW power consumption. The comparator uses a current-mirrorbased positive feedback and hysteresis to generate the mV-range threshold. It has three new ideas: (1) to use the input signal to bias the current mirror, which only activates the current mirror when the input signal reaches a detectable threshold; (2) to achieve dynamically controllable detectable threshold by using control signals to adjust the mirror transistor sizes; and (3) to use negative feedback to compensate the process-voltagetemperature variation. Preliminary SPICE simulation results using state-of-the-art 9HP (BiCMOS) have shown that the proposed hysteresis-based comparator can achieve the following performance metrics: 1) Very low comparator threshold (in the range of mV); furthermore, these threshold voltages can be programmable at run-time from a few to tens of mV. 2) Steep equivalent subthreshold slope in the range of sub-mV/decade. 3) Ultra-low leakage power (in the sub-nW range for a 0.1mV input voltage) and switching energy (in the nW range). The proposed hysteresis-based comparator only requires one standard logic supply source (working over 1V to 0.5V). Furthermore, initial simulations have shown that this comparator threshold is reliable over the process and voltage (PV) variations, and linearly proportional to temperature (T) variation.

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