A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM

Walter, Dennis; Scharfe, Andre; Oefelein, Alexander; Schraut, Florian; Bauer, Heiner; Csaszar, Farkas; Niebsch, Robert; Schreiter, Jörg; Eisenreich, Holger; Höppner, Sebastian

doi:10.1109/coolchips49199.2020.9097639

Cited by 9 publications

(4 citation statements)

References 6 publications

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“…As an outlook for future improvements, we performed a trial synthesis of the OPC UA engine with cell libraries characterized for adaptive reverse body bias 3 . This methods is very effective at reducing leakage [12], and would help scenarios with low duty cycles where the OPC UA engine remains mostly idle. Our preliminary results indicate that the OPC UA engine could be implemented at 50 MHz and 0.55 V with only 50 µW leakage, a reduction by more than half.…”

Section: Measurement Resultsmentioning

confidence: 99%

Hardware Implementation of an OPC UA Server for Industrial Field Devices

Bauer,

Höppner,

Iatrou

et al. 2021

Preprint

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Industrial plants suffer from a high degree of complexity and incompatibility in their communication infrastructure, caused by a wild mix of proprietary technologies. This prevents transformation towards Industry 4.0 and the Industrial Internet of Things. Open Platform Communications Unified Architecture (OPC UA) is a standardized protocol that addresses these problems with uniform and semantic communication across all levels of the hierarchy. However, its adoption in embedded field devices, such as sensors and actors, is still lacking due to prohibitive memory and power requirements of software implementations. We have developed a dedicated hardware engine that offloads processing of the OPC UA protocol and enables realization of compact and low-power field devices with OPC UA support. As part of a proof-of-concept embedded system we have implemented this engine in a 22 nm FDSOI technology. We measured performance, power consumption, and memory footprint of our test chip and compared it with a software implementation based on open62541 and a Raspberry Pi 2B. Our OPC UA hardware engine is 50 times more energy efficient and only requires 36 KiB of memory. The complete chip consumes only 24 mW under full load, making it suitable for low-power embedded applications.

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Section: Measurement Resultsmentioning

confidence: 99%

Hardware Implementation of an OPC UA Server for Industrial Field Devices

Bauer,

Höppner,

Iatrou

et al. 2021

Preprint

Self Cite

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“…A comparison is performed in terms of several key parameters, shown in Table 2, to highlight the performance characteristics of MCUs with volatile SRAM and nvSRAM based on emerging memories [19,20,64,[66][67][68][69][70]. Conventional SRAM consumes a much higher retention current than the deep-sleep-mode current required by sensor networks and energy-management systems, particularly as process geometry scales down.…”

Section: Characteristics Of Various Storage Typesmentioning

confidence: 99%

“…However, these transistors generally cause an increase in memory macro area and active power dissipation, requiring additional techniques for minimizing cell size and active energy. An ultra-low-voltage MCU featuring single-rail SRAM was developed using 22 nm FDX technology and an adaptive reverse body bias scheme, achieving a leakage power of 6.6 µW and active power of 6.3 µW/MHz [67]. Nevertheless, the single rail macro incurs a 20% area overhead compared to the dual rail macro, and a custom bitcell design is needed to ensure stable read operations down to 0.5 V, thereby amplifying the complexity of the design.…”

Section: Characteristics Of Various Storage Typesmentioning

confidence: 99%

A Survey of Emerging Memory in a Microcontroller Unit

Qi,

Fan,

Cai

et al. 2024

Micromachines

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In the era of widespread edge computing, energy conservation modes like complete power shutdown are crucial for battery-powered devices, but they risk data loss in volatile memory. Energy autonomous systems, relying on ambient energy, face operational challenges due to power losses. Recent advancements in emerging nonvolatile memories (NVMs) like FRAM, RRAM, MRAM, and PCM offer mature solutions to sustain work progress with minimal energy overhead during outages. This paper thoroughly reviews utilizing emerging NVMs in microcontroller units (MCUs), comparing their key attributes to describe unique benefits and potential applications. Furthermore, we discuss the intricate details of NVM circuit design and NVM-driven compute-in-memory (CIM) architectures. In summary, integrating emerging NVMs into MCUs showcases promising prospects for next-generation applications such as Internet of Things and neural networks.

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“…SpiNNaker 2 will be implemented in GLOBAL-FOUNDRIES 22FDX technology [14]. This FDSOI technology allows the application of adaptive body biasing (ABB) for low-power operation at ultra-low supply voltages in both forward [15] and reverse bias schemes [16]. For maximum energy efficiency and reasonable clock frequencies, 0.50V nominal supply voltage is chosen and ABB in a forward bias scheme is applied.…”

Section: The Spinnaker 2 Prototype Chip a System Overviewmentioning

confidence: 99%

Low-Power Low-Latency Keyword Spotting and Adaptive Control with a SpiNNaker 2 Prototype and Comparison with Loihi

Yan,

Stewart,

Choo

et al. 2020

Preprint

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We implemented two neural network based benchmark tasks on a prototype chip of the second-generation SpiN-Naker (SpiNNaker 2) neuromorphic system: keyword spotting and adaptive robotic control. Keyword spotting is commonly used in smart speakers to listen for wake words, and adaptive control is used in robotic applications to adapt to unknown dynamics in an online fashion. We highlight the benefit of a multiplyaccumulate (MAC) array in the SpiNNaker 2 prototype which is ordinarily used in rate-based machine learning networks when employed in a neuromorphic, spiking context. In addition, the same benchmark tasks have been implemented on the Loihi neuromorphic chip, giving a side-by-side comparison regarding power consumption and computation time. While Loihi shows better efficiency when less complicated vector-matrix multiplication is involved, with the MAC array, the SpiNNaker 2 prototype shows better efficiency when high dimensional vector-matrix multiplication is involved.

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A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM

Cited by 9 publications

References 6 publications

Hardware Implementation of an OPC UA Server for Industrial Field Devices

Hardware Implementation of an OPC UA Server for Industrial Field Devices

A Survey of Emerging Memory in a Microcontroller Unit

Low-Power Low-Latency Keyword Spotting and Adaptive Control with a SpiNNaker 2 Prototype and Comparison with Loihi

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