A 0.52 <i>μ</i>W, 38 nV/√Hz Chopper Amplifier With a Low-Noise DC Servo Loop, an Embedded Ripple Reduction Loop, and a Squeezed Inverter Stage

Pham, Xuan Thanh; Nguyen, Van Nhan; Kim, Jie-Seok; Lee, Jong‐Wook

doi:10.1109/tcsii.2020.3045491

Cited by 11 publications

(7 citation statements)

References 12 publications

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“…v 2 n contains a bias-dependent thermal noise and area-dependent flicker noise, resulting in design trade-offs between noise and power/area. According to (19), the input differential pair is crucial for noise optimization. In this design, input transistors M P1 and M article has been accepted for inclusion in a future issue of this journal.…”

Section: Circuit Design Of a Chopper Ccia With Vm-dslmentioning

confidence: 99%

“…DSL circuits provide an efficient way to remove the EDO, however, they also have drawbacks. One of its major drawbacks is the introduction of additional electronic noise, which can easily become detrimental to low-noise biosensor applications as demonstrated in [4], [17], [18], and [19]. While significant effort has been devoted to the noise analysis and optimization of chopper amplifiers [4], [16], [20], [21], a comprehensive analysis of the noise contribution of the DSL has not been widely investigated.…”

Section: Introductionmentioning

confidence: 99%

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Noise Analysis and Design Methodology of Chopper Amplifiers With Analog DC-Servo Loop for Biopotential Acquisition Applications

Huang,

Rodriguez

2024

IEEE Trans. VLSI Syst.

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Biopotential acquisition chopper instrumentation amplifiers require a dc-servo loop (DSL) in order to filter electrode dc offsets. However, the noise performance degradation due to the addition of the DSL is often overlooked despite that it can be very detrimental at the frequencies of interest. This article presents an in-depth noise analysis of biopotential acquisition chopper instrumentation amplifiers with analog DSLs. Analytical expressions that predict the noise of different DSL implementations are found and a design flow to minimize their noise contribution is proposed. The design methodology is demonstrated with example circuits targeting biopotential recording systems. These circuits are implemented using a standard 180 nm CMOS technology, and their performance is verified through postlayout simulations. The findings of this work provide a comprehensive understanding of the noise characteristics of a DSL, its impact on noise performance, and design strategies for noise optimization.

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Section: Circuit Design Of a Chopper Ccia With Vm-dslmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Noise Analysis and Design Methodology of Chopper Amplifiers With Analog DC-Servo Loop for Biopotential Acquisition Applications

Huang,

Rodriguez

2024

IEEE Trans. VLSI Syst.

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“…The multi-stage CCIA proposed in this work has a flexible bandwidth from 0.2 to 10 kHz thanks to the programmable Miller compensation capacitors C C1,2 . In contrast, previous designs [16,17], which also use a multi-stage circuit in the main path, use fixed values of the Miller compensation components so that the bandwidth of these designs is 0.67 and 0.8 kHz, respectively. The midband gain of the CCIA is determined by the ratio of the input capacitances C in1,2 and the feedback capacitances C fb1,2 .…”

Section: Squeezed-inverter Amplifiermentioning

confidence: 99%

Ultra-Low Power Programmable Bandwidth Capacitively-Coupled Chopper Instrumentation Amplifier Using 0.2 V Supply for Biomedical Applications

Pham

Kieu

Hoàng

2023

JLPEA

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This paper presents a capacitively coupled chopper instrumentation amplifier (CCIA) with ultra-low power consumption and programmable bandwidth for biomedical applications. To achieve a flexible bandwidth from 0.2 to 10 kHz without additional power consumption, a programmable Miller compensation technique was proposed and used in the CCIA. By using a Squeezed inverter amplifier (SQI) that employs a 0.2-V supply, the proposed CCIA addresses the primary noise source in the first stage, resulting in high noise power efficiency. The proposed CCIA is designed using a 0.18 µm CMOS technology process and has a chip area of 0.083 mm2. With a power consumption of 0.47 µW at 0.2 and 0.8 V supply, the proposed amplifier architecture achieves a thermal noise of 28 nV/√Hz, an input-related noise (IRN) of 0.9 µVrms, a closed-loop gain (AV) of 40 dB, a power supply rejection ratio (PSRR) of 87.6 dB, and a common-mode rejection ratio (CMRR) of 117.7 dB according to post-simulation data. The proposed CCIA achieves a noise efficiency factor (NEF) of 1.47 and a power efficiency factor (PEF) of 0.56, which allows comparison with the latest research results.

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“…However, the bandwidth was strictly limited by 200 Hz 10 . More recently, several very promising works have been published using more advanced semiconductor technologies and more complex design concepts in order to even further reduce input noise and offset, while also dealing with chopping‐related challenges 11–25 …”

Section: Utilizing Chopping For Input Noise and Input Offset Reductionmentioning

confidence: 99%

“…10 More recently, several very promising works have been published using more advanced semiconductor technologies and more complex design concepts in order to even further reduce input noise and offset, while also dealing with chopping-related challenges. [11][12][13][14][15][16][17][18][19][20][21][22][23][24][25] In general, one typically distinguishes between (1) pure or classical chopping as employed in this work, which is partially extended to nested chopping using several interleaved choppers 3,26 ; (2) chopper stabilization, which is a multipath amplifier approach utilizing a main amplifier and a nulling amplifier 27 ; and (3) analogous auto zeroing, for example, using switched capacitors. Although the basic principle of the latter is different, it is still related to this topic, since the inputs are switched and input offset is reduced.…”

Section: Theoretical Backgroundmentioning

confidence: 99%

Chopping for over 50 MHz gain‐bandwidth product current sense amplifiers achieving input noise level of 8.5 nV/√Hz

Matthus

Ellinger

2022

Circuit Theory & Apps

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An accurate, high-speed, fully differential difference amplifier for current sensing utilizing the chopper approach was implemented in a 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology. Unlike state-of-the-art solutions, we use a higher chopping frequency in the MHz range due to the bandwidth requirements of the introduced circuits for the latter application, namely, low-side phase-current measurement in motor control circuits. Except the low-pass filter (LPF) effect of the output stage, no additional LPF was integrated in hardware at the output of the circuits. We show that on the other hand a digital LPF, which can be integrated in the field-programmable gatearray (FPGA) logic or microcontroller used for the motor control, offers a higher flexibility in terms of filter design. Weak input signals of only few mV can be reconstructed with a high accuracy. This is demonstrated for a 500 kHz rectangular signal and a chopping frequency of 20 MHz. Note that an inputsignal frequency of several hundreds of kHz with harmonics in the MHz region is very challenging for chopper amplifiers. Still, a significant decrease of the input-referred noise is demonstrated, especially cancelling out the 1/f-noise achieving a remaining noise floor of approximately 8.5 nV/√Hz. Overall, the input-referred noise level can be pushed far below 50 μV (root mean square).Moreover, using a quite relaxed second-order Butterworth filter with a 3 dB corner frequency of 1 MHz, input-referred noise levels of 10 μV (root mean square) can be easily achieved at the costs of reduced bandwidth. The lowest achieved input offset is 50 μV. The gain is adjusted by resistive feedback and is approximately 40 dB. Hence, the amplifier is suitable for current sensing in motor control circuits, and a significant reduction of the shunt resistance typically used for this purpose will be possible.

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A 0.52 μW, 38 nV/√Hz Chopper Amplifier With a Low-Noise DC Servo Loop, an Embedded Ripple Reduction Loop, and a Squeezed Inverter Stage

Cited by 11 publications

References 12 publications

Noise Analysis and Design Methodology of Chopper Amplifiers With Analog DC-Servo Loop for Biopotential Acquisition Applications

Noise Analysis and Design Methodology of Chopper Amplifiers With Analog DC-Servo Loop for Biopotential Acquisition Applications

Ultra-Low Power Programmable Bandwidth Capacitively-Coupled Chopper Instrumentation Amplifier Using 0.2 V Supply for Biomedical Applications

Chopping for over 50 MHz gain‐bandwidth product current sense amplifiers achieving input noise level of 8.5 nV/√Hz

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