A 0.5 V Inverter-Based Analog Output-Capacitorless Low-Dropout Regulator with Bulk-Driven Transient-Enhancing Paths

Lee, Jinhen; Chan, P.K.

doi:10.1109/icccas55266.2022.9824861

Cited by 3 publications

(4 citation statements)

References 11 publications

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“…Based on the above analysis, a dual loop LDO is proposed to achieve fast-transient and high PSR. The proposed LDO is based on the concept described in [23][24][25][26][27], which focuses on the slew-rate improvement. In order to improve the PSR performance, in this work, a high gain loop is added.…”

Section: Fast-transient Dual Loop Ldo With High Psrmentioning

confidence: 99%

A fast-transient dual loop LDO with high PSR

Fang,

Jin,

Liu

et al. 2024

IEICE Electron. Express

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In this work, the design of a 0.18μm CMOS dual loop capacitor-less low-dropout regulator (LDO) to achieve fast-transient response and good power supple rejection (PSR) is proposed for system-on-chip (SoC) power supply. The proposed LDO has a high slew-rate fast loop for enhancing transient response capability, and the high gain slow loop to improve PSR. Results show that the LDO consumes 100μA quiescent current, delivering a 50mA load current over a 30pF load. The maximum transient output-voltage variation is within 10% of the output voltage with recovery time of less than 81ns with a load step between 500μA and 50mA with 50ns edge times. The PSR is better than 50dB at 1MHz.

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Section: Fast-transient Dual Loop Ldo With High Psrmentioning

confidence: 99%

A fast-transient dual loop LDO with high PSR

Fang,

Jin,

Liu

et al. 2024

IEICE Electron. Express

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“…However, its gain and driving capabilities are low. For this reason, the bulk-drain-driven [22] differential pairs are introduced to obtain the design tradeoff between the gate-source or bulk-driven techniques. This can offer an improved IMCR with respect to that of the gate-source driven technique, whilst the transconductance is not reduced significantly due to weak degeneration arising from bulk-drain transistor topology.…”

Section: Proposed Four-stage Amplifier With Cross-feedforward Positiv...mentioning

confidence: 99%

“…As a result of this weak degeneration, the amplifier's parameters such as noise, gain, and bandwidth are still higher than that of bulk-driven circuits. Furthermore, in comparison with bulk-drain-driven circuits, the temperature effect of bulk-driven is less obvious [22]. As a result, the bulk-drain-driven circuit can provide a compromising design solution among the transconductance and signal swing in low-voltage design.…”

Section: Proposed Four-stage Amplifier With Cross-feedforward Positiv...mentioning

confidence: 99%

“…The use of native transistors (with negative threshold voltage) ensures low-voltage operation. As such, the use of diode-based transistors permits attenuation of any spike [22] that appears through the transition change of transconductance from the complementary differential pairs. This reduced spike will not overdrive the subsequent stage, thus does not jeopardize the amplification in the next circuit stage.…”

Section: Proposed Four-stage Amplifier With Cross-feedforward Positiv...mentioning

confidence: 99%

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A 0.5-V Four-Stage Amplifier Using Cross-Feedforward Positive Feedback Frequency Compensation

Gao,

Chan

2023

Chips

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This paper presents a low-voltage CMOS four-stage amplifier operating in the subthreshold region. The first design technique includes the cross-feedforward positive feedback frequency compensation (CFPFC) for obtaining better bandwidth efficiency in a low-voltage multi-stage amplifier. The second design technique incorporates both the bulk-drain-driven input stage topology in conjunction with a low-voltage attenuator to permit operation at a low voltage, and improves the input common-mode range (ICMR). The proposed circuit is implemented using TSMC-40 nm process technology. It consumes 0.866 μW at a supply voltage of 0.5 V. With a capacitive load of 50 pF, this four-stage amplifier can achieve 84.59 dB in gain, 161.00 kHz in unity-gain bandwidth, 96 deg in phase margin, and 5.7 dB in gain margin whilst offering an input-referred noise of 213.63 nV/Hz @1 kHz, small-signal power-bandwidth FoMss of 9.31 (MHz∙pF/μW), and noise-power per bandwidth-based FoMnpb of 1.15 × 10−6 ((µV/Hz)·µW/Hz). Compared to the conventional bulk-driven input stage design technique, it offers improved multi-parameter performance metrics in terms of noise, power, and bandwidth at a compromising tradeoff on ICMR with respect to bulk-driven amplifier design. Compared with conventional gate-source input stage design, it offers improved ICMR. The amplifier is useful for low-voltage analog signal-processing applications.

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A fully integrated fast transient response digital low-dropout regulator with built-in sampling clock

Xin

Wang

et al. 2023

Microelectronics Journal

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A 0.5 V Inverter-Based Analog Output-Capacitorless Low-Dropout Regulator with Bulk-Driven Transient-Enhancing Paths

Cited by 3 publications

References 11 publications

A fast-transient dual loop LDO with high PSR

A fast-transient dual loop LDO with high PSR

A 0.5-V Four-Stage Amplifier Using Cross-Feedforward Positive Feedback Frequency Compensation

A fully integrated fast transient response digital low-dropout regulator with built-in sampling clock

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